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rev. 4109h?8051?01/05 1. features mpeg i/ii-layer 3 hardwired decoder ? stand-alone mp3 decoder ? 48, 44.1, 32, 24, 22.05, 16 khz sampling frequency ? separated digital volume control on left and right channels (software control using 31 steps) ? bass, medium, and treble control (31 steps) ? bass boost sound effect ? ancillary data extraction ? crc error and mpeg frame synchronization indicators programmable audio output for interfacing with common audio dac ? pcm format compatible ?i 2 s format compatible 8-bit mcu c51 core based (f max = 20 mhz) 2304 bytes of internal ram 64k bytes of code memory ? at89c51snd1c: flash (100k erase/write cycles) ? at83snd1c: rom 4k bytes of boot flash memory (at89c51snd1c) ? isp: download from usb (standard) or uart (option) external code memory ? at80c51snd1c: romless usb rev 1.1 controller ? full speed data transmission built-in pll ? mp3 audio clocks ?usb clock multimedia card ? interface compatibility atmel dataflash ? spi interface compatibility ide/atapi interface 2 channels 10-bit adc, 8 khz (8-true bit) ? battery voltage monitoring ? voice recording controlled by software up to 44 bits of general-purpose i/os ? 4-bit interrupt keyboard port for a 4 x n matrix ?smartmedia ? software interface 2 standard 16-bit timers/counters hardware watchdog timer standard full duplex uart with baud rate generator two wire master and slave modes controller spi master and slave modes controller power management ? power-on reset ? software programmable mcu clock ? idle mode, power-down mode operating conditions: ?3v, 10%, 25 ma typical operating at 25c ? temperature range: -40 c to +85 c packages ? tqfp80, bga81, plcc84 (development board) ?dice single-chip flash microcontroller with mp3 decoder and human interface at83snd1c at89c51snd1c at80c51snd1c
2 at8xc51snd1c 4109h?8051?01/05 2. description the at8xc51snd1c are fully integrated stand-alone hardwired mpeg i/ii-layer 3 decoder with a c51 microcontroller core handling data flow and mp3-player control. the at89c51snd1c includes 64k bytes of flash memory and allows in-system pro- gramming through an embedded 4k bytes of boot flash memory. the at83snd1c includes 64k bytes of rom memory. the at80c51snd1c does not include any code memory. the at8xc51snd1c include 2304 bytes of ram memory. the at8xc51snd1c provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (usb, twi, spi, ide), adc input, i 2 s output, and all external memory interface (nand or nor flash, smartmedia, multimedia, dataflash cards). 3. typical applications mp3-player pda, camera, mobile phone mp3 car audio/multimedia mp3 home audio/multimedia mp3 4. block diagram figure 1. at8xc51snd1c block diagram 8-bit internal bus clock and pll unit c51 (x2 core) ram 2304 bytes flash rom interrupt handler unit filt x2 x1 mp3 decoder unit twi controller mmc interface i/o scl sda mdat p0-p5 10-bit a to d converter vss vdd keyboard interface kin3:0 i 2 s/pcm audio interface avss avdd 1 alternate function of port 1 ain1:0 ports int0 int1 mosi miso 3 alternate function of port 3 4 alternate function of port 4 timers 0/1 t1 t0 spi/dataflash controller mclk mcmd sck rst aref dsel dclk sclk dout 64 kbytes usb controller d+ d- uart rxd txd ide interface ss watchdog flash boot 4 kbytes isp uvss uvdd and brg ale 33 33 3 3444411 1
3 at8xc51snd1c 4109h?8051?01/05 5. pin description 5.1 pinouts figure 1. at8xc51snd1c 80-pin qfp package notes: 1. isp pin is only available in at89c51snd1c product. do not connect this pin on at83snd1c product. 2. psen pin is only available in at80c51snd1c product. at89c51snd1c-ro (flash) at83snd1c-ro (rom) at80c51snd1c-ro (romless) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.0/rxd 1 2 3 4 5 6 7 8 13 11 10 p2.2/a1 0 p2.3/a1 1 p2.4/a1 2 p2.6/a1 4 p2.5/a1 3 p2.7/a1 5 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p0.0/ad0 pvss vss x2 x1 tst vss 9 12 14 15 16 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd p3.7/rd p3.6/wr p3.5/t1 vdd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pvdd vdd p1.6/scl 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80 ale isp 1 /psen 2 /nc uvdd uvss p5.0 p5.1 p4.7 p4.6 d- d+ p5.3 p5.2 vss vdd p4.5 p4.4
4 at8xc51snd1c 4109h?8051?01/05 figure 2. at8xc51snd1c 81-pin bga package notes: 1. isp pin is only available in at89c51snd1c product. do not connect this pin on at83snd1c and at80c51snd1c product. 2. psen pin is only available in at80c51snd1c product. p5.0 8 9765432 c b a d e f g h 1 ale p1.1 p1.4 vdd x2 vss uvdd d+ isp 1 / p1.5 x1 pvss tst d- vss p0.0/ p1.0/ p1.7/ pvdd uvss vdd p3.1/ p3.0/ p0.2/ p5.1 p1.6/ filt p3.4/ p3.5/ p3.3/ p3.2/ vdd p0.1/ vss p0.5/ avdd p3.7/ ain0 p3.6/ p4.2/ p4.3/ p0.6 p0.7/ p2.7/ mdat p5.3 avss arefn p4.0/ p4.1/ p2.1/ p4.5 vss mclk dout ain1 arefp p2.0/ p4.7 p2.2/ p2.6/ p2.3/ mcmd sclk vss p5.2 p4.6 p4.4 p2.5/ p2.4/ vdd rst dsel dclk vdd j kin0 p1.3/ kin3 p1.2/ kin2 ss mosi miso sck ad2 p0.3/ ad3 a8 p0.4/ ad4 ad0 ad1 ad7 ad5 a9 a10 a12 a11 a13 a14 a15 scl sda rxd txd int0 int1 t1 t0 rd wr psen 2 nc
5 at8xc51snd1c 4109h?8051?01/05 figure 3. at8xc51snd1c 84-pin plcc package at89c51snd1c-sr (flash) p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.2/int0 65 64 63 62 61 60 59 58 55 56 57 12 13 14 15 16 17 22 20 19 33 34 35 36 37 4 3 2 1 84 83 82 81 80 79 78 nc p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p5.0 pavss vss x2 nc x1 p3.1/txd 18 21 23 24 25 38 39 40 41 42 69 68 67 66 70 5 6 7 8 9 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd vss vdd p3.7/rd p3.0/rxd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pavdd vdd p1.6/scl 26 43 tst p5.2 p0.0/ad0 77 p2.2/a10 54 ale isp nc p5.1 p4.7 p4.6 76 75 10 11 28 27 29 30 31 32 uvdd uvss 44 45 46 47 48 49 50 51 52 53 74 73 72 71 p4.4 p4.5 vdd vss d- d+ nc p5.3
6 at8xc51snd1c 4109h?8051?01/05 5.2 signals all the at8xc51snd1c signals are detailed by functionality in table 3 to table 16. table 3. ports signal description table 4. clock signal description signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.7:0 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin3:0 scl sda p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.7:0 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.7:0 i/o port 4 p4 is an 8-bit bidirectional i/o port with internal pull-ups. miso mosi sck ss p5.3:0 i/o port 5 p5 is a 4-bit bidirectional i/o port with internal pull-ups. - signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crys tal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crys tal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. -
7 at8xc51snd1c 4109h?8051?01/05 table 5. timer 0 and timer 1 signal description table 6. audio interface signal description table 7. usb controller signal description signal name type description alternate function int0 i timer 0 gate input int0 serves as external run contro l for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0 . if bit it0 is cleared, bit ie0 is set by a low level on int0 . p3.2 int1 i timer 1 gate input int1 serves as external run contro l for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1 . if bit it1 is cleared, bit ie1 is set by a low level on int1 . p3.3 t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 signal name type description alternate function dclk o dac data bit clock - dout o dac audio data - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchronized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k ? pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port -
8 at8xc51snd1c 4109h?8051?01/05 table 8. mutimediacard interface signal description table 9. uart signal description table 10. spi controller signal description table 11. twi controller signal description signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bidirectional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bidirectional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p4.0 mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p4.1 sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p4.2 ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p4.3 signal name type description alternate function scl i/o twi serial clock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sda i/o twi serial data sda is the bidirectional two wire data line. p1.7
9 at8xc51snd1c 4109h?8051?01/05 table 12. a/d converter signal description table 13. keypad interface signal description table 14. external access signal description notes: 1. for rom/flash dice product versions: pad ea must be connected to vcc. 2. for romless dice product versions: pad ea must be connected to vss. signal name type description alternate function ain1:0 i a/d converter analog inputs - arefp i analog positive voltage reference input - arefn i analog negative voltage reference input this pin is internally connected to avss. - signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the external memory or the ide interface. p0.7:0 ale o address latch enable output ale signals the start of an external bus cycle and indicates that valid address information is available on lines a7:0. an external latch is used to demultiplex the address from address/data bus. - psen i/o program store enable output (at80c51snd1c only) this signal is active low during ex ternal code fetch or external code read (movc instruction). - isp i/o isp enable input (at89c51snd1c only) this signal must be held to gnd through a pull-down resistor at the falling reset to force execution of the internal bootloader. - rd o read signal read signal asserted during external data memory read operation. p3.7 wr o write signal write signal asserted during external data memory write operation. p3.6 ea (1)(2) i external access enable (dice only) ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. -
10 at8xc51snd1c 4109h?8051?01/05 table 15. system signal description table 16. power signal description signal name type description alternate function rst i reset input holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down re sistor which allows the device to be reset by connecting a capacitor between this pin and v dd . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . - signal name type description alternate function vdd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - avdd pwr analog supply voltage connect this pin to +3v supply voltage. - avss gnd analog ground connect this pin to ground. - pvdd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - uvdd pwr usb supply voltage connect this pin to +3v supply voltage. - uvss gnd usb ground connect this pin to ground. -
11 at8xc51snd1c 4109h?8051?01/05 5.17 internal pin structure table 18. detailed internal pin structure notes: 1. for information on resistors value, input/output levels, and drive capability, refer to the section ?dc characteristics?, page 184. 2. when the two wire controller is enabled, p 1 , p 2 , and p 3 transistors are disabled allowing pseudo open-drain structure. 3. in port 2, p 1 transistor is continuously driven when outputting a high level bit address (a15:8). circuit (1) type pins input tst input/output rst input/output p1 (2) p2 (3) p3 p4 p53:0 input/output p0 mcmd mdat isp psen output ale sclk dclk dout dsel mclk input/output d+ d- r tst vdd r rst vss p vdd watchdog output p 3 vss n p 1 vdd vdd 2 osc latch output periods p 2 vdd vss n p vdd vss n p vdd d+ d-
12 at8xc51snd1c 4109h?8051?01/05 6. clock controller the at8xc51snd1c clock controller is based on an on-chip oscillator feeding an on- chip phase lock loop (pll). all internal clocks to the peripherals and cpu core are generated by this controller. 6.1 oscillator the at8xc51snd1c x1 and x2 pins are the input and the output of a single-stage on- chip inverter (see figure 4) that can be configured with off-chip components such as a pierce oscillator (see figure 5). value of capacitors and crystal characteristics are detailed in the section ?dc characteristics?, page 163. the oscillator outputs three different clocks: a clock for the pll, a clock for the cpu core, and a clock for the peripherals as shown in figure 4. these clocks are either enabled or disabled, depending on the power reduction mode as detailed in the section ?power management? on page 48. the peripheral clock is used to generate the timer 0, timer 1, mmc, adc, spi, and port sampling clocks. figure 4. oscillator block diagram and symbol figure 5. crystal connection 6.2 x2 feature unlike standard c51 products that require 12 oscillator clock periods per machine cycle, the at8xc51snd1c need only 6 oscillator cloc k periods per machine cycle. this fea- ture called the ?x2 feature? can be enabled using the x2 bit (1) in ckcon (see table 5) and allows the at8xc51snd1c to operate in 6 or 12 oscillator clock periods per machine cycle. as shown in figure 4, bot h cpu and peripheral clocks are affected by this feature. figure 6 shows the x2 mode switching waveforms. after reset the standard mode is activated. in standard mode the cpu and peripheral clock frequency is the oscillator frequency divided by 2 while in x2 mode, it is the oscillator frequency. note: 1. the x2 bit reset value depends on the x2b bit in the hardware security byte (see table 12 on page 24). using the at89c51snd1c (flash version) the system can boot either in standard or x2 mode depending on the x2b value. using at83snd1c (rom version) the system always boots in standard mode. x2b bit can be changed to x2 mode later by software. x1 x2 pd pcon.1 idl pcon.0 peripheral cpu core 0 1 x2 ckcon.0 2 per clock clock clock peripheral clock symbol cpu clock cpu core clock symbol osc clock oscillator clock symbol oscillator clock vss x1 x2 q c1 c2
13 at8xc51snd1c 4109h?8051?01/05 figure 6. mode switching waveforms note: 1. in order to prevent any incorrect operation while operating in x2 mode, user must be aware that all peripherals using clock frequency as time reference (timers, etc.) will have their time reference divided by 2. for example, a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. 6.3 pll 6.3.1 pll description the at8xc51snd1c pll is used to generate internal high frequency clock (the pll clock) synchronized with an external low-frequency (the oscillator clock). the pll clock provides the mp3 decoder, the audio interface, and the usb interface clocks. figure 7 shows the internal structure of the pll. the pfld block is the phase frequency comparator and lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock coming from the r divider and generates some pulses on the up or down signal depending on the edge position of the reverse clock. the pllen bit in pllcon register is used to enable the clock generation. when the pll is locked, the bit plock in pllcon register (see table 6) is set. the chp block is the charge pump that generates the voltage reference for the vco by injecting or extracting charges from the external filter connected on pfilt pin (see figure 8). value of the filter components are detailed in the section ?dc characteristics?. the vco block is the voltage controlled oscillator controlled by the voltage v ref pro- duced by the charge pump. it generates a square wave signal: the pll clock. figure 7. pll block diagram and symbol x1 2 x1 clock x2 bi t x2 mode (1) std mode std mode pllen pllcon.1 n6:0 n divider r divider vco pllclk oscclk r 1 + () n1 + ---------------------------------------------- - = osc clock pfld plock pllcon.0 pfilt chp vref up down r9:0 pll clock pll clock symbol pll cloc k
14 at8xc51snd1c 4109h?8051?01/05 figure 8. pll filter connection 6.3.2 pll programming the pll is programmed using the flow shown in figure 9. as soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. the pll clock frequency will depend on mp3 decoder clock and audio interface clock frequencies. figure 9. pll programming flow vss filt r c1 c2 vss pll programming configure dividers n6:0 = xxxxxxb r9:0 = xxxxxxxxxxb enable pll pllres = 0 pllen = 1 pll locked? plock = 1?
15 at8xc51snd1c 4109h?8051?01/05 6.4 registers table 5. ckcon register ckcon (s:8fh) ? clock control register reset value = 0000 000xb (at89c51snd1c) or 0000 0000b (at83snd1c) table 6. pllcon register pllcon (s:e9h) ? pll control registe r 76543210 twix2 wdx2 - six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7twix2 two-wire clock control bit set to select the oscillator clock divided by 2 as twi clock input (x2 independent). clear to select the peripheral clock as twi clock input (x2 dependent). 6wdx2 watchdog clock control bit set to select the oscillator clock divided by 2 as watchdog clock input (x2 independent). clear to select the peripheral clock as watchdog clock input (x2 dependent). 5- reserved the values read from this bit is indeterminate. do not set this bit. 4six2 enhanced uart clock (mode 0 and 2) control bit set to select the oscillator clock divided by 2 as uart clock input (x2 independent). clear to select the peripheral clock as uart clock input (x2 dependent).. 3- reserved the values read from this bit is indeterminate. do not set this bit. 2t1x2 timer 1 clock control bit set to select the oscillator clock divided by 2 as timer 1 clock input (x2 independent). clear to select the peripheral clock as timer 1 clock input (x2 dependent). 1t0x2 timer 0 clock control bit set to select the oscillator clock divided by 2 as timer 0 clock input (x2 independent). clear to select the peripheral clock as timer 0 clock input (x2 dependent). 0x2 system clock control bit clear to select 12 clock periods per machine cycle (std mode, f cpu = f per = f osc / 2). set to select 6 clock periods per machine cycle (x2 mode, f cpu = f per = f osc ). 76543210 r1 r0 - - pllres - pllen plock bit number bit mnemonic description 7 - 6 r1:0 pll least significant bits r divider 2 lsb of the 10-bit r divider. 5 - 4 - reserved the values read from these bits are always 0. do not set these bits. 3 pllres pll reset bit set this bit to reset the pll. clear this bit to free the pll and allow enabling.
16 at8xc51snd1c 4109h?8051?01/05 reset value = 0000 1000b table 7. pllndiv register pllndiv (s:eeh) ? pll n divider register reset value = 0000 0000b table 8. pllrdiv register pllrdiv (s:efh) ? pll r divider register reset value = 0000 0000b 2- reserved the value read from this bit is always 0. do not set this bit. 1 pllen pll enable bit set to enable the pll. clear to disable the pll. 0plock pll lock indicator set by hardware when pll is locked. clear by hardware w hen pll is unlocked. 76543210 - n6n5n4n3n2n1n0 bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6 - 0 n6:0 pll n divider 7 - bit n divider. 76543210 r9 r8 r7 r6 r5 r4 r3 r2 bit number bit mnemonic description 7 - 0 r9:2 pll most significant bits r divider 8 msb of the 10-bit r divider. bit number bit mnemonic description
17 at8xc51snd1c 4109h?8051?01/05 7. program/code memory the at8xc51snd1c execute up to 64k bytes of program/code memory. figure 10 shows the split of internal and external program/code memory spaces depending on the product. the at83snd1c product provides the internal program/code memory in rom memory while the at89c51snd1c product provides it in flash memory. these 2 products do not allow external code memory execution. external code memory execution is achieved using the at80c51snd 1c product which does not provide any internal pro- gram/code memory. the flash memory increases eprom and rom functionality by in-circuit electrical era- sure and programming. the high voltage needed for programming or erasing flash cells is generated on-chip using the standard v dd voltage, made possible by the internal charge pump. thus, the at89c51snd1c can be programmed using only one voltage and allows in-application software programming. hardware programming mode is also available using common programming tools. see the application note ?programming t89c51x and at89c51x with device programmers?. the at89c51snd1c implements an additional 4k bytes of on-chip boot flash memory provided in flash memory. this boot memory is delivered programmed with a standard boot loader software allowing in-system programming (isp). it also contains some application programming interface routines named api routines allowing in application programming (iap) by using user?s own boot loader. figure 10. program/code memory organization 4k bytes boot flash ffffh f000h 0000h 64k bytes code flash ffffh at89c51snd1c 0000h 64k bytes code rom ffffh at83snd1c f000h 0000h 64k bytes external code ffffh at80c51snd1c
18 at8xc51snd1c 4109h?8051?01/05 7.1 romless memory architecture as shown in figure 11 the at80c51snd1c external memory is composed of one space detailed in the following paragraph. figure 11. at80c51snd1c memory architecture 7.1.1 user space this space is composed of a 64k bytes code (flash, eeprom, eprom?) memory. it contains the user?s application code. 7.1.2 memory interface the external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (psen , and ale). figure 12 shows the structure of the external address bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed with a7:0 on p0. table 12 describes the external memory interface signals. figure 12. external code memory interface structure ffffh 64k bytes external memory 0000h use r table 2. external code memory interface signals signal name type description alternate function a15:8 o address lines upper address lines fo r the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals indicates that valid address information are available on lines ad7:0. - psen o program store enable output (at80c51snd1c only) this signal is active low during exte rnal code fetch or external code read (movc instruction). - flash eprom at80c51snd1c p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale latch oe psen
19 at8xc51snd1c 4109h?8051?01/05 7.2.1 external bus cycles this section describes the bus cycles the at80c51snd1c executes to fetch code (see figure 13) in the external program/code memory. external memory cycle takes 6 cpu clock periods. this is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in x2 mode. for further information on x2 mode see section ?clock ?. for simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and does not provide precise timing information. for bus cycling parameters refer to the ?ac-dc parameters? section. figure 13. external code fetch waveforms 7.3 rom memory architecture as shown in figure 14 the at83snd1c rom memory is composed of one space detailed in the following paragraph. figure 14. at83snd1c memory architecture 7.3.1 user space this space is composed of a 64k bytes rom memory programmed during the manu- facturing process. it contains the user?s application code. 7.4 flash memory architecture as shown in figure 15 the at89c51snd1c flash memory is composed of four spaces detailed in the following paragraphs. ale p0 p2 psen pcl pch pch pcl d7:0 d7:0 pch d7:0 cpu clock ffffh 64k bytes rom memory 0000h user
20 at8xc51snd1c 4109h?8051?01/05 figure 15. at89c51snd1c memory architecture 7.4.1 user space this space is composed of a 64k bytes fl ash memory organized in 512 pages of 128 bytes. it contains the user?s application code. this space can be read or written by both software and hardware modes. 7.4.2 boot space this space is composed of a 4k bytes flash memory. it contains the boot loader for in- system programming and the routines for in application programming. this space can only be read or written by hardware mode using a parallel programming tool. 7.4.3 hardware security space this space is composed of one byte: the ha rdware security byte (hsb see table 12) divided in 2 separate nibbles. the msn contains the x2 mode configuration bit and the boot loader jump bit as detailed in section ?boot memory execution?, page 21 and can be written by software while the lsn contains the lock system level to protect the mem- ory content against piracy as detailed in section ?hardware security system?, page 21 and can only be written by hardware. 7.4.4 extra row space this space is composed of 2 bytes: the software boot vector (sbv, see table 13). this byte is used by the software boot loader to build the boot address. the software security byte (ssb, see table 14). this byte is used to lock the execution of some boot loader commands. ffffh 64k bytes flash memory 0000h hardware security user 4k bytes flash memory ffffh f000h boo t extra row
21 at8xc51snd1c 4109h?8051?01/05 7.5 hardware security system the at89c51snd1c implements three lock bits lb2:0 in the lsn of hsb (see table 12) providing three levels of security for user?s program as described in table 12 while the at83snd1c is always set in read disabled mode. level 0 is the level of an erased part and does not enable any security feature. level 1 locks the hardware programming of both user and boot memories. level 2 locks also hardware verifying of both user and boot memories level 3 locks also the external execution. notes: 1. u means unprogrammed, p means programmed and x means don?t care (pro- grammed or unprogrammed). 2. lb2 is not implemented in the at8xc51snd1c products. 3. at89c51snd1c products are delivered with third level programmed to ensure that the code programmed by software using isp or user?s boot loader is secured from any hardware piracy. 7.7 boot memory execution as internal c51 code space is limited to 64k bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from f000h to ffffh. the boot memory is enabled by setting the enboot bit in auxr1 (see figure 10). the three ways to set this bit are detailed in the following sections. 7.7.1 software boot mapping the software way to set enboot consists in writing to auxr1 from the user?s soft- ware. this enables boot loader or api routines execution. 7.7.2 hardware condition boot mapping the hardware condition is based on the isp pin. when driving this pin to low level, the chip reset sets enboot and forces the reset vector to f000h instead of 0000h in order to execute the boot loader software. as shown in figure 16 the hardware condition always allows in-system recovery when user?s memory has been corrupted. 7.7.3 programmed condition boot mapping the programmed condition is based on the boot loader jump bit (bljb) in hsb. as shown in figure 16 when this bit is programmed (by hardware or software programming mode), the chip reset set enboot and forces the reset vector to f000h instead of 0000h, in order to execute the boot loader software. table 6. lock bit features (1) level lb2 (2) lb1 lb0 internal execution external execution hardware verifying hardware programming software programming 0 u u u enable enable enable enable enable 1 u u p enable enable enable disable enable 2 u p x enable enable disable disable enable 3 (3) p x x enable disable disable disable enable
22 at8xc51snd1c 4109h?8051?01/05 figure 16. hardware boot process algorithm the software process (boot loader) is detailed in the ?boot loader datasheet? document. 7.8 preventing flash corruption see section ?reset recommendation to prevent flash corruption?, page 49. atmel?s boot loader hardware software hard cond? isp = l? reset hard cond init enboot = 1 pc = f000h fcon = 00h prog cond? bljb = p? standard init enboot = 0 pc = 0000h fcon = f0h prog cond init enboot = 1 pc = f000h fcon = f0h user?s application process process
23 at8xc51snd1c 4109h?8051?01/05 7.9 registers table 10. auxr1 register auxr1 (s:a2h) ? auxiliary register 1 reset value = xxxx 00x0b note: 1. enboot bit is only available in at89c51snd1c product. 76543210 - - enboot - gf3 0 - dps bit number bit mnemonic description 7 - 6 - reserved the value read from these bits are indeterminate. do not set these bits. 5 enboot 1 enable boot flash set this bit to map the boot flash in the code space between at addresses f000h to ffffh. clear this bit to disable boot flash. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf3 general flag this bit is a general-purpose user flag. 20 always zero this bit is stuck to logic 0 to allow inc auxr1 instruction without affecting gf3 flag. 1- reserved for data pointer extension. 0dps data pointer select bit set to select second data pointer: dptr1. clear to select first data pointer: dptr0.
24 at8xc51snd1c 4109h?8051?01/05 7.11 hardware bytes table 12. hsb byte ? hardware security byte reset value = xxuu uxxx, uuuu uuuu after an hardware full chip erase. note: 1. x2b initializes the x2 bit in ckcon during the reset phase. 2. in order to ensure boot loader activation at first power-up, at89c51snd1c products are delivered with bljb programmed. 3. bits 0 to 3 (lsn) can only be programmed by hardware mode. reset value = xxxx xxxx, uuuu uuuu after an hardware full chip erase. reset value = xxxx xxxx, uuuu uuuu after an hardware full chip erase. 76543210 x2b bljb - - - lb2 lb1 lb0 bit number bit mnemonic description 7x2b (1) x2 bit program this bit to start in x2 mode. unprogram (erase) this bit to start in standard mode. 6bljb (2) boot loader jump bit program this bit to execute the boot loader at address f000h on next reset. unprogram (erase) this bit to execut e user?s application at address 0000h on next reset. 5 - 4 - reserved the value read from these bits is alwa ys unprogrammed. do not program these bits. 3- reserved the value read from this bit is always unprogrammed. do not program this bit. 2 - 0 lb2:0 hardware lock bits refer to for bits description. table 13. sbv byte ? software boot vector 76543210 add15 add14 add13 add12 add11 add10 add9 add8 bit number bit mnemonic description 7 - 0 add15:8 msb of the user?s boot loader 16-bit address location refer to the boot loader datasheet for usage information (boot loader dependent) table 14. ssb byte ? software security byte 76543210 ssb7ssb6ssb5ssb4ssb3ssb2ssb1ssb0 bit number bit mnemonic description 7 - 0 ssb7:0 software security byte data refer to the boot loader datasheet for usage information (boot loader dependent)
25 at8xc51snd1c 4109h?8051?01/05 8. data memory the at8xc51snd1c provides data memory access in 2 different spaces: 1. the internal space mapped in three separate segments: ? the lower 128 bytes ram segment ? the upper 128 bytes ram segment ? the expanded 2048 bytes ram segment 2. the external space. a fourth internal segment is available but dedicated to special function registers, sfrs, (addresses 80h to ffh) accessible by direct addressing mode. for information on this segment, refer to the section ?special function registers?, page 32. figure 17 shows the internal and external data memory spaces organization. figure 17. internal and external data memory organization 8.1 internal space 8.1.1 lower 128 bytes ram the lower 128 bytes of ram (see figure 18) are accessible from address 00h to 7fh using direct or indirect addressing modes. the lowest 32 bytes are grouped into 4 banks of 8 registers (r0 to r7). 2 bits rs0 and rs1 in psw register (see table 8) select which bank is in use according to table 2. this allows more efficient use of code space, since register instructions are shorte r than instructions that use direct address- ing, and can be used for context switching in interrupt service routines. table 2. register bank selection the next 16 bytes above the register banks form a block of bit-addressable memory space. the c51 instruction set includes a wi de selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h to 7fh. 2k bytes upper 128 bytes internal ram lower 128 bytes internal ram special function registers 80h 80h 00h 7ffh ffh 00h ffh 64k bytes external xram 0000h ffffh direct addressing addressing 0800h 7fh internal eram direct or indirect indirect addressing extram = 0 extram = 1 rs1 rs0 description 0 0 register bank 0 from 00h to 07h 0 1 register bank 1 from 08h to 0fh 1 0 register bank 2 from 10h to 17h 1 1 register bank 3 from 18h to 1fh
26 at8xc51snd1c 4109h?8051?01/05 figure 18. lower 128 bytes internal ram organization 8.2.1 upper 128 bytes ram the upper 128 bytes of ram are accessible from address 80h to ffh using only indirect addressing mode. 8.2.2 expanded ram the on-chip 2k bytes of expanded ram (eram) are accessible from address 0000h to 07ffh using indirect addressing mode through movx instructions. in this address range, extram bit in auxr register (see table 9) is used to select the eram (default) or the xram. as shown in figure 17 when extram = 0, the eram is selected and when extram = 1, the xram is selected (see section ?external space?). the eram memory can be resized using xrs1:0 bits in auxr register to dynamically increase external access to the xram space. table 3 details the selected eram size and address range. table 3. eram size selection note: lower 128 bytes ram, upper 128 bytes ram, and expanded ram are made of volatile memory cells. this means that the ram content is indeterminate after power-up and must then be initialized properly. bit-addressable space 4 banks of 8 registers r0-r7 30h 7fh (bit addresses 0-7fh) 20h 2fh 18h 1fh 10h 17h 08h 0fh 00h 07h xrs1 xrs0 eram size address 0 0 256 bytes 0 to 00ffh 0 1 512 bytes 0 to 01ffh 1 0 1k byte 0 to 03ffh 1 1 2k bytes 0 to 07ffh
27 at8xc51snd1c 4109h?8051?01/05 8.4 external space 8.4.1 memory interface the external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (rd , wr , and ale). figure 19 shows the structure of the external address bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed with a7:0 on p0. table 5 describes the external memory interface signals. figure 19. external data memory interface structure table 5. external data memory interface signals 8.5.1 page access mode the at8xc51snd1c implement a feature called page access that disables the output of dph on p2 when executing movx @dptr instruction. page access is enable by setting the dphdis bit in auxr register. page access is useful when application uses both eram and 256 bytes of xram. in this case, software modifies intensively extram bit to select access to eram or xram and must save it if used in interrupt service routine. page access allows external access above 00ffh address without generating dph on p2. thus eram is accessed using movx @ri or movx @dptr with dptr < 0100h, < 0200h, < 0400h or < 0800h depending on the xrs1:0 bits value. then xram is accessed using movx @dptr with dptr 0800h regardless of xrs1:0 bits value while keeping p2 for general i/o usage. signal name type description alternate function a15:8 o address lines upper address lines fo r the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals indicates that valid address information are available on lines ad7:0. - rd o read read signal output to external data memory. p3.7 wr o write write signal output to external memory. p3.6 ram peripheral at8xc51snd1c p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale wr oe rd wr latch
28 at8xc51snd1c 4109h?8051?01/05 8.5.2 external bus cycles this section describes the bus cycles the at8xc51snd1c executes to read (see figure 20), and write data (see figure 21) in the external data memory. external memory cycle takes 6 cpu clock periods. this is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in x2 mode. for further infor- mation on x2 mode, refer to the section ?x2 feature?, page 12. slow peripherals can be accessed by stretching the read and write cycles. this is done using the m0 bit in auxr register. setting this bit changes the width of the rd and wr signals from 3 to 15 cpu clock periods. for simplicity, figure 20 and figure 21 depict the bus cycle waveforms in idealized form and do not provide precise timing information. for bus cycle timing parameters refer to the section ?ac characteristics?. figure 20. external data read waveforms notes: 1. rd signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page access mode), p2 outputs sfr content instead of dph. figure 21. external data write waveforms notes: 1. wr signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page access mode), p2 outputs sfr content instead of dph. ale p0 p2 rd (1) dpl or ri d7:0 dph or p2 (2),(3) p2 cpu clock ale p0 p2 wr (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3)
29 at8xc51snd1c 4109h?8051?01/05 8.6 dual data pointer 8.6.1 description the at8xc51snd1c implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. dptr0 and dptr1 are seen by the cpu as dptr and are accessed using the sfr addresses 83h and 84h that are the dph and dpl addresses. the dps bit in auxr1 register (see table 10) is used to select whether dptr is the data pointer 0 or the data pointer 1 (see figure 22). figure 22. dual data pointer implementation 8.6.2 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ?) are well served by using one data pointer as a ?source? pointer and the other one as a ?destina- tion? pointer. below is an example of block move impl ementation using the 2 pointers and coded in assembler. the latest c compiler also takes advantage of this feature by providing enhanced algorithm libraries. the inc instruction is a short (2 bytes) and fast (6 cpu clocks) way to manipulate the dps bit in the auxr1 register. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence mat- ters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. ; ascii block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; ends when encountering null character ; note: dps exits opposite of entry state unless an extra inc auxr1 is added auxr1 equ 0a2h move: mov dptr,#source ; address of source inc auxr1 ; switch data pointers mov dptr,#dest ; address of dest mv_loop: inc auxr1 ; switch data pointers movx a,@dptr ; get a byte from source inc dptr ; increment source address inc auxr1 ; switch data pointers movx @dptr,a ; write the byte to dest inc dptr ; increment dest address jnz mv_loop ; check for null terminator end_move: 0 1 dph0 dph1 dpl0 0 1 dps auxr1.0 dph dpl dpl1 dptr dptr0 dptr1
30 at8xc51snd1c 4109h?8051?01/05 8.7 registers table 8. psw register psw (s:8eh) ? program status word register reset value = 0000 0000b 76543210 cy ac f0 rs1 rs0 ov f1 p bit number bit mnemonic description 7cy carry flag carry out from bit 1 of alu operands. 6ac auxiliary carry flag carry out from bit 1 of addition operands. 5f0 user definable flag 0 4 - 3 rs1:0 register bank select bits refer to table 2 for bits description. 2ov overflow flag overflow set by arithmetic operations. 1f1 user definable flag 1 0p parity bit set when acc contains an odd number of 1?s. cleared when acc contains an even number of 1?s.
31 at8xc51snd1c 4109h?8051?01/05 table 9. auxr register auxr (s:8eh) ? auxiliary control register reset value = x000 1101b 76543210 - ext16 m0 dphdis xrs1 xrs0 extram ao bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6ext16 external 16-bit access enable bit set to enable 16-bit access mode during movx instructions. clear to disable 16-bit access mode and enable standard 8-bit access mode during movx instructions. 5m0 external memory access stretch bit set to stretch rd or wr signals duration to 15 cpu clock periods. clear not to stretch rd or wr signals and set duration to 3 cpu clock periods. 4 dphdis dph disable bit set to disable dph output on p2 when executing movx @dptr instruction. clear to enable dph output on p2 when executing movx @dptr instruction. 3 - 2 xrs1:0 expanded ram size bits refer to table 3 for eram size description. 1extram external ram enable bit set to select the external xram when executing movx @ri or movx @dptr instructions. clear to select the internal expanded ram when executing movx @ri or movx @dptr instructions. 0ao ale output enable bit set to output the ale signal only during movx instructions. clear to output the ale signal at a constant rate of f cpu /3.
32 at8xc51snd1c 4109h?8051?01/05 9. special function registers the special function registers (sfrs) of the at8xc51snd1c derivatives fall into the categories detailed in table 1 to table 17. the relative addresses of these sfrs are provided together with their reset values in table 18. in this table, the bit-addressable registers are identified by note 1. note: 1. enboot bit is only available in at89c51snd1c product. table 1. c51 core sfrs mnemonicaddname 76543210 acc e0h accumulator b f0h b register psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer dpl 82h data pointer low byte dph 83h data pointer high byte table 2. system management sfrs mnemonicaddname 76543210 pcon 87h power control smod1 smod0 - - gf1 gf0 pd idl auxr 8eh auxiliary register 0 - ext16 m0 dphdis xrs1 xrs0 extram ao auxr1 a2h auxiliary register 1 - - enboot (1) -gf30 -dps nvers fbh version number nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 table 3. pll and system clock sfrs mnemonicaddname 76543210 ckcon8fhclock control -------x2 pllcon e9h pll control r1 r0 - - pllres - pllen plock pllndiv eeh pll n divider - n6 n5 n4 n3 n2 n1 n0 pllrdiv efh pll r divider r9 r8 r7 r6 r5 r4 r3 r2 table 4. interrupt sfrs mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea eaud emp3 es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 - eusb - ekb eadc espi ei2c emmc iph0 b7h interrupt priority control high 0 - iphaud iphmp3 iphs ipht1 iphx1 ipht0 iphx0 ipl0 b8h interrupt priority control low 0 - iplaud iplmp3 ipls iplt1 iplx1 iplt0 iplx0 iph1 b3h interrupt priority control high 1 - iphusb - iphkb iphadc iphspi iphi2c iphmmc ipl1 b2h interrupt priority control low 1 - iplusb - iplkb ipladc iplspi ipli2c iplmmc
33 at8xc51snd1c 4109h?8051?01/05 note: 1. fcon register is only available in at89c51snd1c product. table 5. port sfrs mnemonicaddname 76543210 p0 80h 8-bit port 0 p1 90h 8-bit port 1 p2 a0h 8-bit port 2 p3 b0h 8-bit port 3 p4 c0h 8-bit port 4 p5 d8h4-bit port 5 ---- table 6. flash memory sfr mnemonicaddname 76543210 fcon (1) d1h flash control fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy table 7. timer sfrs mnemonicaddname 76543210 tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 tl0 8ah timer/counter 0 low byte th0 8ch timer/counter 0 high byte tl1 8bh timer/counter 1 low byte th1 8dh timer/counter 1 high byte wdtrst a6h watchdog timer reset wdtprg a7h watchdog timer program -----wto2wto1wto0
34 at8xc51snd1c 4109h?8051?01/05 table 8. mp3 decoder sfrs mnemonicaddname 76543210 mp3con aah mp3 control mpen mpbbst crcen mskanc mskreq msklay msksyn mskcrc mp3sta c8h mp3 status mpanc mpreq errlay errsyn errcrc mpfs1 mpfs0 mpver mp3sta1 afh mp3 status 1 - - - mpfreq mpbreq - - - mp3dat ach mp3 data mpd7 mpd6 mpd5 mpd4 mpd3 mpd2 mpd1 mpd0 mp3anc adh mp3 ancillary data and7 and6 and5 and4 and3 and2 and1 and0 mp3vol 9eh mp3 audio volume control left - - - vol4 vol3 vol2 vol1 vol0 mp3vor 9fh mp3 audio volume control right - - - vor4 vor3 vor2 vor1 vor0 mp3bas b4h mp3 audio bass control - - - bas4 bas3 bas2 bas1 bas0 mp3med b5h mp3 audio medium control - - - med4 med3 med2 med1 med0 mp3tre b6h mp3 audio treble control - - - tre4 tre3 tre2 tre1 tre0 mp3clk ebh mp3 clock divider - - - mpcd4 mpcd3 mpcd2 mpcd1 mpcd0 table 9. audio interface sfrs mnemonicaddname 76543210 audcon0 9ah audio control 0 just4 just3 just2 just1 just0 pol dsiz hlr audcon1 9bh audio control 1 src drqen msreq mudrn - dup1 dup0 auden audsta 9ch audio status sreq udrn aubusy ----- auddat 9dh audio data aud7 aud6 aud5 aud4 aud3 aud2 aud1 aud0 audclk ech audio clock divider - - - aucd4 aucd3 aucd2 aucd1 aucd0
35 at8xc51snd1c 4109h?8051?01/05 table 10. usb controller sfrs mnemonicaddname 76543210 usbcon bch usb global control usbe suspclk sdrmwup - uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 usbint bdh usb global interrupt - - wupcpu eorint sofint - - spint usbien beh usb global interrupt enable - - ewupcpu eeorint esofint - - espint uepnumc7husb endpoint number ------epnum1epnum0 uepconx d4h usb endpoint x control epen nakien nakout nakin dtgl epdir eptype1 eptype0 uepstax ceh usb endpoint x status dir rxoutb1 stallrq txrdy stlcrc rxsetup rxoutb0 txcmp ueprstd5husb endpoint reset -----ep2rstep1rstep0rst uepintf8husb endpoint interrupt -----ep2intep1intep0int uepien c2h usb endpoint interrupt enable -----ep2inteep1inteep0inte uepdatx cfh usb endpoint x fifo data fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 ubyctx e2h usb endpoint x byte counter - byct6 byct5 byct4 byct3 byct2 byct1 byct0 ufnuml bah usb frame number low fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 ufnumh bbh usb frame number high - - crcok crcerr - fnum10 fnum9 fnum8 usbclkeahusb clock divider ------usbcd1usbcd0 table 11. mmc controller sfrs mnemonicaddname 76543210 mmcon0 e4h mmc control 0 drptr dtptr crptr ctptr mblock dfmt rfmt crcdis mmcon1 e5h mmc control 1 blen3 blen2 blen1 blen0 datdir daten respen cmden mmcon2 e6h mmc control 2 mmcen dcr ccr - - datd1 datd0 flowc mmsta deh mmc control and status - - cbusy crc16s datfs crc7s respfs cflck mmint e7h mmc interrupt mcbi eori eoci eofi f2fi f1fi f2ei f1ei mmmsk dfh mmc interrupt mask mcbm eorm eocm eofm f2fm f1fm f2em f1em mmcmd ddh mmc command mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 mmdat dch mmc data md7 md6 md5 md4 md3 md2 md1 md0 mmclk edh mmc clock divider mmcd7 mmcd6 mmcd5 mmcd4 mmcd3 mmcd2 mmcd1 mmcd0 table 12. ide interface sfr mnemonicaddname 76543210 dat16h f9h high order data byte d15 d14 d13 d12 d11 d10 d9 d8
36 at8xc51snd1c 4109h?8051?01/05 table 13. serial i/o port sfrs mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer saden b9h slave address mask saddr a9h slave address bdrcon 92h baud rate control brr tbck rbck spd src brl 91h baud rate reload table 14. spi controller sfrs mnemonicaddname 76543210 spcon c3h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spstac4hspi status spifwcol-modf---- spdat c5h spi data spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 table 15. two wire controller sfrs mnemonicaddname 76543210 sscon 93h synchronous serial control sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 sssta 94h synchronous serial status ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 ssdat 95h synchronous serial data ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 ssadr 96h synchronous serial address ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssgc table 16. keyboard interface sfrs mnemonicaddname 76543210 kbcon a3h keyboard control kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 kbsta a4h keyboard status kpde - - - kinf3 kinf2 kinf1 kinf0 table 17. a/d controller sfrs mnemonicaddname 76543210 adcon f3h adc control - adidl aden adeoc adsst - - adcs adclk f2h adc clock divider - - - adcd4 adcd3 adcd2 adcd1 adcd0 addlf4hadc data low byte ------adat1adat0 addh f5h adc data high byte adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2
37 at8xc51snd1c 4109h?8051?01/05 reserved notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. nvers reset value depends on the silicon version: 1000 0100 for at89c51snd1c product and 0000 0001 for at83snd1c product. 3. fcon register is only available in at89c51snd1c product. 4. fcon reset value is 00h in case of reset with hardware condition. 5. ckcon reset value depends on the x2b bit (programmed or unprogrammed) in the hardware byte. table 18. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 dat16h xxxx xxxx nvers xxxx xxxx (2) ffh f0h b (1) 0000 0000 adclk 0000 0000 adcon 0000 0000 addl 0000 0000 addh 0000 0000 f7h e8h pllcon 0000 1000 usbclk 0000 0000 mp3clk 0000 0000 audclk 0000 0000 mmclk 0000 0000 pllndiv 0000 0000 pllrdiv 0000 0000 efh e0h acc (1) 0000 0000 ubyctlx 0000 0000 mmcon0 0000 0000 mmcon1 0000 0000 mmcon2 0000 0000 mmint 0000 0011 e7h d8h p5 (1) xxxx 1111 mmdat 1111 1111 mmcmd 1111 1111 mmsta 0000 0000 mmmsk 1111 1111 dfh d0h psw (1) 0000 0000 fcon (3) 1111 0000 (4) uepconx 1000 0000 ueprst 0000 0000 d7h c8h mp3sta (1) 0000 0001 uepstax 0000 0000 uepdatx xxxx xxxx cfh c0h p4 (1) 1111 1111 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat xxxx xxxx usbaddr 0000 0000 uepnum 0000 0000 c7h b8h ipl0 (1) x000 0000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0001 0000 bfh b0h p3 (1) 1111 1111 ien1 0000 0000 ipl1 0000 0000 iph1 0000 0000 mp3bas 0000 0000 mp3med 0000 0000 mp3tre 0000 0000 iph0 x000 0000 b7h a8h ien0 (1) 0000 0000 saddr 0000 0000 mp3con 0011 1111 mp3dat 0000 0000 mp3anc 0000 0000 mp3sta1 0100 0001 afh a0h p2 (1) 1111 1111 auxr1 xxxx 00x0 kbcon 0000 1111 kbsta 0000 0000 wdtrst xxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx audcon0 0000 1000 audcon1 1011 0010 audsta 1100 0000 auddat 1111 1111 mp3vol 0000 0000 mp3vor 0000 0000 9fh 90h p1 (1) 1111 1111 brl 0000 0000 bdrcon xxx0 0000 sscon 0000 0000 sssta 1111 1000 ssdat 1111 1111 ssadr 1111 1110 97h 88h tcon (1) 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr x000 1101 ckcon 0000 000x (5) 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00xx 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
38 at8xc51snd1c 4109h?8051?01/05 10. interrupt system the at8xc51snd1c, like other control-oriented computer architectures, employ a pro- gram interrupt method. this operation branches to a subroutine and performs some service in response to the interrupt. when the subroutine completes, execution resumes at the point where the interrupt occurred. interrupts may occur as a result of internal at8xc51snd1c activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard). in all cases, interrupt operation is pro- grammed by the system designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routines. all of the interrupt sources are enabled or disabled by the system designer and may be manipulated dynamically. a typical interrupt event chain occurs as follows: an internal or external device initiates an interrupt-request signal. the at8xc51snd1c, latches this event into a flag buffer. the priority of the flag is compared to the priority of other interrupts by the interrupt handler. a high priority causes the handler to set an interrupt flag. this signals the instruction execution unit to execute a context switch. this context switch breaks the current flow of instruction sequences. the execution unit completes the current instruction prior to a save of the program counter (pc) and reloads the pc with the start address of a software service routine. the software service routine executes assigned tasks and as a final activity performs a reti (return from interrupt) instruction. this instruction signals completion of the interrupt, resets the interrupt-in-progress priority and reloads the program counter. program operation then continues from the original point of interruption. table 1. interrupt system signals six interrupt registers are used to control the interrupt system. 2 8-bit registers are used to enable separately the interrupt sources: ien0 and ien1 registers (see table 7 and table 8). four 8-bit registers are used to establish the priority level of the different sources: iph0, ipl0, iph1 and ipl1 registers (see table 9 to table 12). 10.2 interrupt system priorities each of the interrupt sources on the at8xc51snd1c can be individually programmed to one of four priority levels. this is accomplished by one bit in the interrupt priority high registers (iph0 and iph1) and one bit in the interrupt priority low registers (ipl0 and ipl1). this provides each interrupt source four possible priority levels according to table 3. signal name type description alternate function int0 i external interrupt 0 see section "external interrupts", page 41. p3.2 int1 i external interrupt 1 see section ?external interrupts?, page 41. p3.3 kin3:0 i keyboard interrupt inputs see section ?keyboard interface?, page 182. p1.3:0
39 at8xc51snd1c 4109h?8051?01/05 table 3. priority levels a low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. higher priority interrupts are serviced before lower priority interrupts. the response to simultaneous occurrence of equal priority inter- rupts is determined by an internal hardware polling sequence detailed in table 4. thus, within each priority level there is a second priority structure determined by the polling sequence. the interrupt control system is shown in figure 23. table 4. priority within same level iphxx iplxx priority level 0 0 0 lowest 011 102 1 1 3 highest interrupt name priority number interrupt address vectors interrupt request flag cleared by hardware (h) or by software (s) int0 0 (highest priority) c:0003h h if edge, s if level timer 0 1 c:000bh h int1 2 c:0013h h if edge, s if level timer 1 3 c:001bh h serial port 4 c:0023h s mp3 decoder 5 c:002bh s audio interface 6 c:0033h s mmc interface 7 c:003bh s two wire controller 8 c:0043h s spi controller 9 c:004bh s a to d converter 10 c:0053h s keyboard 11 c:005bh s reserved 12 c:0063h - usb 13 c:006bh s reserved 14 (lowest priority) c:0073h -
40 at8xc51snd1c 4109h?8051?01/05 figure 23. interrupt control system ei2c ien1.1 emmc ien1.0 eusb ien1.6 espi ien1.2 ex0 ien0.0 00 01 10 11 external interrupt 0 int0 ea ien0.7 ex1 ien0.2 external interrupt 1 int1 et0 ien0.1 timer 0 emp3 ien0.5 mp3 decoder et1 ien0.3 timer 1 eaud ien0.6 audio interface eadc ien1.3 a to d converter spi controller usb controller ekb ien1.4 keyboard mmc controller twi controller iph/l interrupt enable lowest priority interrupts highest kin3:0 priority enable sck si so scl sda 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 priority interrup ts es ien0.4 serial port 00 01 10 11 txd rxd mclk mdat mcmd ain1:0 d+ d-
41 at8xc51snd1c 4109h?8051?01/05 10.5 external interrupts 10.5.1 int1:0 inputs external interrupts int0 and int1 (intn , n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits it0 and it1 (itn, n = 0 or 1) in tcon register as shown in figure 24. if itn = 0, intn is triggered by a low level at the pin. if itn = 1, intn is negative-edge triggered. external interrupts are enabled with bits ex0 and ex1 (exn, n = 0 or 1) in ien0. events on intn set the interrupt request flag ien in tcon register. if the interrupt is edge-triggered, the request flag is cleared by hard- ware when vectoring to the interrupt service routine. if the interrupt is level-triggered, the interrupt service routine must clear the request flag and the interrupt must be deas- serted before the end of the interrupt service routine. int0 and int1 inputs provide both the capability to exit from power-down mode on low level signals as detailed in section ?exiting power-down mode?, page 50. figure 24. int1:0 input circuitry 10.5.2 kin3:0 inputs external interrupts kin0 to kin3 provide the capability to connect a matrix keyboard. for detailed information on these inputs, refer to section ?keyboard interface?, page 182. 10.5.3 input sampling external interrupt pins (int1:0 and kin3:0) are sampled once per peripheral cycle (6 peripheral clock periods) (see figure 25). a level-triggered interrupt pin held low or high for more than 6 peripheral clo ck periods (12 oscillator in standard mode or 6 oscillator clock periods in x2 mode) guarantees detection. edge-triggered external interrupts must hold the request pin low for at least 6 peripheral clock periods. figure 25. minimum pulse timings 0 1 int0/1 it0/1 tcon.0/2 ex0/1 ien0.0/2 int0/1 interrup t reques t ie0/1 tcon.1/3 edge-triggered interrupt level-triggered interrupt 1 cycle 1 cycle > 1 peripheral cycle 1 cycle > 1 peripheral cycle
42 at8xc51snd1c 4109h?8051?01/05 10.6 registers table 7. ien0 register ien0 (s:a8h) ? interrupt enable register 0 reset value = 0000 0000b 76543210 ea eaud emp3 es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit set to enable all interrupts. clear to disable all interrupts. if ea = 1, each interrupt source is i ndividually enabled or disabled by setting or clearing its interrupt enable bit. 6 eaud audio interface interrupt enable bit set to enable audio interface interrupt. clear to disable audio interface interrupt. 5emp3 mp3 decoder interrupt enable bit set to enable mp3 decoder interrupt. clear to disable mp3 decoder interrupt. 4es serial port interrupt enable bit set to enable serial port interrupt. clear to disable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit set to enable timer 1 overflow interrupt. clear to disable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit set to enable external interrupt 1. clear to disable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit set to enable timer 0 overflow interrupt. clear to disable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit set to enable external interrupt 0. clear to disable external interrupt 0.
43 at8xc51snd1c 4109h?8051?01/05 table 8. ien1 register ien1 (s:b1h) ? interrupt enable register 1 reset value = 0000 0000b 76543210 - eusb - ekb eadc espi ei2c emmc bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6eusb usb interface interrupt enable bit set this bit to enable usb interrupts. clear this bit to disable usb interrupts. 5- reserved the value read from this bit is always 0. do not set this bit. 4ekb keyboard interface interrupt enable bit set to enable keyboard interrupt. clear to disable keyboard interrupt. 3 eadc a to d converter interrupt enable bit set to enable adc interrupt. clear to disable adc interrupt. 2espi spi controller interrupt enable bit set to enable spi interrupt. clear to disable spi interrupt. 1ei2c two wire controller interrupt enable bit set to enable two wire interrupt. clear to disable two wire interrupt. 0emmc mmc interface interrupt enable bit set to enable mmc interrupt. clear to disable mmc interrupt.
44 at8xc51snd1c 4109h?8051?01/05 table 9. iph0 register iph0 (s:b7h) ? interrupt priority high register 0 reset value = x000 0000b 76543210 - iphaud iphmp3 iphs ipht1 iphx1 ipht0 iphx0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6iphaud audio interface interrupt priority level msb refer to table 3 for priority level description. 5iphmp3 mp3 decoder interrupt priority level msb refer to table 3 for priority level description. 4iphs serial port interrupt priority level msb refer to table 3 for priority level description. 3ipht1 timer 1 interrupt priority level msb refer to table 3 for priority level description. 2iphx1 external interrupt 1 priority level msb refer to table 3 for priority level description. 1ipht0 timer 0 interrupt priority level msb refer to table 3 for priority level description. 0iphx0 external interrupt 0 priority level msb refer to table 3 for priority level description.
45 at8xc51snd1c 4109h?8051?01/05 table 10. iph1 register iph1 (s:b3h) ? interrupt priority high register 1 reset value = 0000 0000b 76543210 - iphusb - iphkb iphadc iphspi iphi2c iphmmc bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6 iphusb usb interrupt priority level msb refer to table 3 for priority level description. 5- reserved the value read from this bit is always 0. do not set this bit. 4iphkb keyboard interrupt priority level msb refer to table 3 for priority level description. 3iphadc a to d converter interrupt priority level msb refer to table 3 for priority level description. 2iphspi spi interrupt priority level msb refer to table 3 for priority level description. 1iphi2c two wire controller interrupt priority level msb refer to table 3 for priority level description. 0iphmmc mmc interrupt priority level msb refer to table 3 for priority level description.
46 at8xc51snd1c 4109h?8051?01/05 table 11. ipl0 register ipl0 (s:b8h) - interrupt priority low register 0 reset value = x000 0000b 76543210 - iplaud iplmp3 ipls iplt1 iplx1 iplt0 iplx0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6iplaud audio interface interrupt priority level lsb refer to table 3 for priority level description. 5iplmp3 mp3 decoder interrupt priority level lsb refer to table 3 for priority level description. 4ipls serial port interrupt priority level lsb refer to table 3 for priority level description. 3iplt1 timer 1 interrupt priority level lsb refer to table 3 for priority level description. 2iplx1 external interrupt 1 priority level lsb refer to table 3 for priority level description. 1iplt0 timer 0 interrupt priority level lsb refer to table 3 for priority level description. 0iplx0 external interrupt 0 priority level lsb refer to table 3 for priority level description.
47 at8xc51snd1c 4109h?8051?01/05 table 12. ipl1 register ipl1 (s:b2h) ? interrupt priority low register 1 reset value = 0000 0000b 76543210 - iplusb - iplkb ipladc iplspi ipli2c iplmmc bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6iplusb usb interrupt priority level lsb refer to table 3 for priority level description. 5- reserved the value read from this bit is always 0. do not set this bit. 4iplkb keyboard interrupt priority level lsb refer to table 3 for priority level description. 3ipladc a to d converter interrupt priority level lsb refer to table 3 for priority level description. 2iplspi spi interrupt priority level lsb refer to table 3 for priority level description. 1ipli2c two wire controller interrupt priority level lsb refer to table 3 for priority level description. 0iplmmc mmc interrupt priority level lsb refer to table 3 for priority level description.
48 at8xc51snd1c 4109h?8051?01/05 11. power management 2 power reduction modes are implemented in the at8xc51snd1c: the idle mode and the power-down mode. these modes are detailed in the following sections. in addition to these power reduction modes, the clocks of the core and peripherals can be dynami- cally divided by 2 using the x2 mode detailed in section ?x2 feature?, page 12. 11.1 reset in order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the rst pin. a bad level leads to a wrong initialization of the internal registers like sfrs, program counter? and to unpredictable behavior of the microcontroller. a proper device reset initializes the at8xc51snd1c and vectors the cpu to address 0000h. rst input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to v dd as shown in figure 26. a warm reset can be applied either directly on the rst pin or indirectly by an internal reset source such as the watchdog timer. resistor val ue and input characteristics are discussed in the section ?dc characteristics? of the at8xc51snd1c datasheet. the status of the port pins during reset is detailed in table 2. figure 26. reset circuitry and power-on reset table 2. pin conditions in special operating modes note: 1. refer to section ?audio output interface?, page 75. 11.2.1 cold reset 2 conditions are required before enabling a cpu start-up: v dd must reach the specified v dd range the level on x1 input pin must be outside the specification (v ih , v il ) if one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywher e in the program space. an active level applied on the rst pin must be maintained till both of the above conditions are met. a reset is active when the level v ih1 is reached and when the pulse width covers the period of time where v dd and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: v dd rise time, oscillator startup time. to determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. table 3 gives some capacitor values examples for a minimum r rst of 50 k ? and different oscillator startup and v dd rise times. mode port 0 port 1 port 2 port 3 port 4 port 5 mmc audio reset floating high high high high high floating 1 idle data data data data data data data data power-down data data data data data data data data r rst rst vss to cpu core and peripherals rst vdd + power-on reset rst input circuitry p vdd from internal reset source
49 at8xc51snd1c 4109h?8051?01/05 table 3. minimum reset capacitor value for a 50 k ? pull-down resistor (1) note: 1. these values assume v dd starts from 0v to the nominal value. if the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence. 11.3.1 warm reset to achieve a valid reset, the reset signal mu st be maintained for at least 2 machine cycles (24 oscillator clock periods) while the os cillator is running. the number of clock periods is mode independent (x2 or x1). 11.3.2 watchdog reset as detailed in section ?watchdog timer?, page 61, the wdt generates a 96-clock period pulse on the rst pin. in order to properly propagate this pulse to the rest of the applica- tion in case of external capacitor or power-supply supervisor circuit, a 1 k ? resistor must be added as shown in figure 27. figure 27. reset circuitry for wdt reset-out usage 11.4 reset recommendation to prevent flash corruption an example of bad initialization situation may occur in an instance where the bit enboot in auxr1 register is initialized from the hardware bit bljb upon reset. since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. if one wants the enboot cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit enboot in sfrs may be set. if the value of program counter is accidently in the range of the boot memory addresses then a flash access (write or erase) may corrupt the flash on-chip memory. it is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off). 11.5 idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, program execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked (refer to section ?oscillator?, page 12). the cpu status before entering idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. the status of the port pins during idle mode is detailed in table 2. oscillator start-up time vdd rise time 1 ms 10 ms 100 ms 5 ms 820 nf 1.2 f 12 f 20 ms 2.7 f 3.9 f 12 f r rst rst vss to cpu core and peripherals vdd + p vdd from wdt reset source vss vdd rst 1k to other on-board circuitry
50 at8xc51snd1c 4109h?8051?01/05 11.5.1 entering idle mode to enter idle mode, the user must set the idl bit in pcon register (see table 8). the at8xc51snd1c enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the at8xc51snd1c enter power-down mode. then it does not go in idle mode when exiting power-down mode. 11.5.2 exiting idle mode there are 2 ways to exit idle mode: 1. generate an enabled interrupt. ? hardware clears idl bit in pcon register which restores the clock to the cpu. execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode. the general-purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred during normal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. ? a logic high on the rst pin clears idl bit in pcon register directly and asynchronously. this restores the clock to the cpu. program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at8xc51snd1c and vectors the cpu to address c:0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. 11.6 power-down mode the power-down mode places the at8xc51snd1c in a very low power state. power- down mode stops the oscillator and freezes all clocks at known states (refer to the sec- tion "oscillator", page 12). the cpu status prior to entering power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of power-down mode. in addition, the sfrs and ram contents are pre- served. the status of the port pins during power-down mode is detailed in table 2. note: v dd may be reduced to as low as v ret during power-down mode to further reduce power dissipation. notice, however, that v dd is not reduced until power-down mode is invoked. 11.6.1 entering power-down mode to enter power-down mode, set pd bit in pcon register. the at8xc51snd1c enters the power-down mode upon execution of the instruction that sets pd bit. the instruction that sets pd bit is the last instruction executed. 11.6.2 exiting power-down mode if v dd was reduced during the power-down mode, do not exit power-down mode until v dd is restored to the normal operating level. there are 2 ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the at8xc51snd1c provides capability to exit from power-down using int0 , int1 , and kin3:0 inputs. in addition, using kin input provides high or low level exit capability (see section ?keyboard interface?, page 182). hardware clears pd bit in pcon register which starts the oscillator and restores the clocks to the cpu and peripherals. using intn input, execution
51 at8xc51snd1c 4109h?8051?01/05 resumes when the input is released (see figure 28) while using kinx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see figure 29). this behavior is necessary for decoding the key while it is still pressed. in both cases, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power-down mode. note: 1. the external interrupt used to exit power-down mode must be configured as level sensitive ( int0 and int1 ) and must be assigned the highest priority. in addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. the execution will only resume when the interrupt is deasserted. 2. exit from power-down by external interrupt does not affect the sfrs nor the internal ram content. figure 28. power-down exit waveform using int1:0 figure 29. power-down exit waveform using kin3:0 note: 1. kin3:0 can be high or low-level triggered. 2. generate a reset. ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscillator and restores the clock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the at8xc51snd1c and vectors the cpu to address 0000h. notes: 1. during the time that execution resumes, the internal ram cannot be accessed; how- ever, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated the power-down mode should not write to a port pin or to the external ram. 2. exit from power-down by reset redefines all the sfrs, but does not affect the internal ram content. int1:0 osc power-down phase oscillator restart phase active phase active phase kin3:0 1 osc power-down phase 1024 clock count active phase active phase
52 at8xc51snd1c 4109h?8051?01/05 11.7 registers table 8. pcon register pcon (s:87h) ? power configuration register reset value = 00xx 0000b 76543210 smod1 smod0 - - gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1,2 or 3. 6smod0 serial port mode bit 0 set to select fe bit in scon register. clear to select sm0 bit in scon register. 5 - 4 - reserved the value read from these bits is indeterminate. do not set these bits. 3gf1 general-purpose flag 1 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 2gf0 general-purpose flag 0 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an in terrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an in terrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence.
53 at8xc51snd1c 4109h?8051?01/05 12. timers/counters the at8xc51snd1c implement 2 general-purpose, 16-bit timers/counters. they are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. when operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. 12.1 timer/counter operations for instance, a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in tcon register (see table 7) turns the timer on by allowing the selected input to increment tlx. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, otherwise, the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided-down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e., f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the timer register counts the negative transitions on the tx external input pin. the external input is sampled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f per /12, i.e., f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. 12.2 timer clock controller as shown in figure 30, the timer 0 (ft0) and timer 1 (ft1) clocks are derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the t0x2 and t1x2 bits in ckcon register. these clocks are issued from the clock controller block as detailed in section ?clock controller?, page 12. when t0x2 or t1x2 bit is set, the timer 0 or timer 1 clock frequency is fixed and equal to the oscillator clock fre- quency divided by 2. when cleared, the timer clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in x2 mode.
54 at8xc51snd1c 4109h?8051?01/05 figure 30. timer 0 and timer 1 clock controller and symbols 12.3 timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 31 through figure 37 show the logical configuration of each mode. timer 0 is controlled by the four lower bits of tmod register (see table 8) and bits 0, 1, 4 and 5 of tcon register (see table 7). tmod register selects the method of timer gat- ing (gate0), timer or counter operation (c/t0#) and mode of operation (m10 and m00). tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0 to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an inter- rupt request. it is important to stop timer/counter before changing mode. 12.3.1 mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (th0 reg- ister) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 31). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 32 gives the overflow period calculation formula. figure 31. timer/counter x (x = 0 or 1) in mode 0 figure 32. mode 0 overflow period formula per clock tim0 clock osc clock 0 1 t0x2 ckcon.1 2 timer 0 clock timer 0 clock symbol per clock tim1 clock osc clock 0 1 t1x2 ckcon.2 2 timer 1 cloc k timer 1 clock symbol timx clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrupt request c/tx# tmod reg thx (8 bits) tlx (5 bits) intx tx 6 ? (16384 ? (thx, tlx)) tfx per = f timx
55 at8xc51snd1c 4109h?8051?01/05 12.3.2 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit ti mer with th0 and tl0 registers connected in cascade (see figure 33). the selected input increments tl0 register. figure 34 gives the overflow period calculation formula when in timer mode. figure 33. timer/counter x (x = 0 or 1) in mode 1 figure 34. mode 1 overflow period formula 12.3.3 mode 2 (8-bit timer with auto-reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see table 9). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 36 gives the autoreload period calculation formula when in timer mode. figure 35. timer/counter x (x = 0 or 1) in mode 2 figure 36. mode 2 autoreload period formula 12.3.4 mode 3 (2 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers (see figure 37). this mode is provided for applications requiring an additional 8- bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod reg- ister, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f tf1 /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg tlx (8 bits) thx (8 bits) intx tx timx clock 6 6 ? (65536 ? (thx, tlx)) tfx per = f timx trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg tlx (8 bits) thx (8 bits) intx tx timx clock 6 tfx per = f timx 6 ? (256 ? thx)
56 at8xc51snd1c 4109h?8051?01/05 3. figure 36 gives the autoreload period calculation formulas for both tf0 and tf1 flags. figure 37. timer/counter 0 in mode 3: 2 8-bit counters figure 38. mode 3 overflow period formula 12.4 timer 1 timer 1 is identical to timer 0 except for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: timer 1 functions as either a timer or event counter in three modes of operation. figure 31 through figure 35 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. timer 1 is controlled by the four high-order bits of tmod register (see figure 8) and bits 2, 3, 6 and 7 of tcon register (see figure 7). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1 to control timer operation. timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. it is important to stop the timer/counter before changing modes. tr0 tcon.4 tf0 tcon.5 int0 0 1 gate0 tmod.3 overflow timer 0 interrup t reques t c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrup t reques t t0 tim0 clock 6 tim0 clock 6 tf0 per = f tim0 6 ? (256 ? tl0) tf1 per = f tim0 6 ? (256 ? th0)
57 at8xc51snd1c 4109h?8051?01/05 12.4.1 mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 31). the upper 3 bits of tl1 register are ignored. prescaler overflow incre- ments th1 register. 12.4.2 mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit ti mer with th1 and tl1 registers connected in cascade (see figure 33). the selected input increments tl1 register. 12.4.3 mode 2 (8-bit timer with auto-reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 register on overflow (see figure 35). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. 12.4.4 mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not available i.e. when timer 0 is in mode 3. 12.5 interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cleared when vectoring to the timer interrupt routine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 39. timer interrupt system tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request
58 at8xc51snd1c 4109h?8051?01/05 12.6 registers table 7. tcon register tcon (s:88h) ? timer/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external interrupt is detected on int1 pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1 ). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external interrupt is detected on int0 pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0 ). set to select falling edge active (edge triggered) for external interrupt 0.
59 at8xc51snd1c 4109h?8051?01/05 notes: 1. reloaded from th1 at overflow. 2. reloaded from th0 at overflow. reset value = 0000 0000b table 9. th0 register th0 (s:8ch) ? timer 0 high byte register reset value = 0000 0000b table 8. tmod register tmod (s:89h) ? timer/counter mode control register 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1 pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1). (1) 1 1 mode 3: timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0 pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1 m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0). (2) 1 1 mode 3: tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0 m00 76543210 -------- bit number bit mnemonic description 7:0 high byte of timer 0
60 at8xc51snd1c 4109h?8051?01/05 table 10. tl0 register tl0 (s:8ah) ? timer 0 low byte register reset value = 0000 0000b table 11. th1 register th1 (s:8dh) ? timer 1 high byte register reset value = 0000 0000b table 12. tl1 register tl1 (s:8bh) ? timer 1 low byte register reset value = 0000 0000b 76543210 -------- bit number bit mnemonic description 7:0 low byte of timer 0 76543210 -------- bit number bit mnemonic description 7:0 high byte of timer 1 76543210 -------- bit number bit mnemonic description 7:0 low byte of timer 1
61 at8xc51snd1c 4109h?8051?01/05 13. watchdog timer the at8xc51snd1c implement a hardware watchdog timer (wdt) that automatically resets the chip if it is allowed to time out. the wdt provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. 13.1 description the wdt consists of a 14-bit prescaler fo llowed by a 7-bit programmable counter. as shown in figure 40, the 14-bit prescaler is fed by the wdt clock detailed in section ?watchdog clock controller?, page 61. the watchdog timer reset register (wdtrst, see table 6) provides control access to the wdt, while the watchdog timer program register (wdtprg, see figure 43) pro- vides time-out period programming. three operations control the wdt: chip reset clears and disables the wdt. programming the time-out value to the wdtprg register. writing a specific 2-byte sequence to the wdtrst register clears and enables the wdt. figure 40. wdt block diagram 13.2 watchdog clock controller as shown in figure 41 the wdt clock (f wdt ) is derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the wtx2 bit in ckcon register. these clocks are issued from the clock c ontroller block as detailed in section "clock controller", page 12. when wtx2 bit is set, the wdt clock frequency is fixed and equal to the oscillator clock frequency divided by 2. when cleared, the wdt clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in x2 mode. figure 41. wdt clock controller and symbol wto2:0 wdtprg.2:0 wdt clock 6 system reset 1eh-e1h decoder wdtrst 14-bit prescaler rst 7-bit counter rst to internal reset en rst match set ov osc clock rst pulse generator per clock wdt clock osc clock 0 1 wtx2 ckcon.6 2 wdt clock wdt clock symbo l
62 at8xc51snd1c 4109h?8051?01/05 13.3 watchdog operation after reset, the wdt is disabled. the wdt is enabled by writing the sequence 1eh and e1h into the wdtrst register. as soon as it is enabled, there is no way except the chip reset to disable it. if it is not cleared us ing the previous sequence, the wdt overflows and forces a chip reset. this overflow generates a high level 96 oscillator periods pulse on the rst pin to globally reset the application (refer to section ?power management?, page 48). the wdt time-out period can be adjusted using wto2:0 bits located in the wdtprg register accordingly to the formula shown in figure 42. in this formula, wtoval repre- sents the decimal value of wto2:0 bits. table 4 reports the time-out period depending on the wdt frequency. figure 42. wdt time-out formula notes: 1. these frequencies are achieved in x1 mode or in x2 mode when wtx2 = 1: f wdt = f osc 2. 2. these frequencies are achieved in x2 mode when wtx2 = 0: f wdt = f osc . 13.4.1 wdt behavior during idle and power-down modes operation of the wdt during power reduction modes deserves special attention. the wdt continues to count while the at8xc51snd1c is in idle mode. this means that you must dedicate some internal or external hardware to service the wdt during idle mode. one approach is to use a peripheral timer to generate an interrupt request when the timer overflows. the interrupt service routine then clears the wdt, reloads the peripheral timer for the next service period and puts the at8xc51snd1c back into idle mode. the power-down mode stops all phase clocks. this causes the wdt to stop counting and to hold its count. the wdt resumes counting from where it left off if the power- down mode is terminated by int0 , int1 or keyboard interrupt. to ensure that the wdt does not overflow shortly after exiting the power-down mode, it is recommended to clear the wdt just before entering power-down mode. the wdt is cleared and disabled if the power-down mode is terminated by a reset. table 4. wdt time-out computation wto2 wto1 wto0 f wdt (ms) 6 mhz (1) 8 mhz (1) 10 mhz (1) 12 mhz (2) 16 mhz (2) 20 mhz (2) 0 0 0 16.38 12.28 9.83 8.19 6.14 4.92 0 0 1 32.77 24.57 19.66 16.38 12.28 9.83 0 1 0 65.54 49.14 39.32 32.77 24.57 19.66 0 1 1 131.07 98.28 78.64 65.54 49.14 39.32 1 0 0 262.14 196.56 157.29 131.07 98.28 78.64 1 0 1 524.29 393.1 314.57 262.14 196.56 157.29 1 1 0 1049 786.24 629.15 524.29 393.12 314.57 1 1 1 2097 1572 1258 1049 786.24 629.15 wdt to = f wdt 6 ? (( 2 14 ? 2 wtoval ) ? 1)
63 at8xc51snd1c 4109h?8051?01/05 13.5 registers table 6. wdtrst register wdtrst (s:a6h write only) ? watchdog timer reset register reset value = xxxx xxxxb figure 43. wdtprg register wdtprg (s:a7h) ? watchdog timer program register reset value = xxxx x000b 76543210 -------- bit number bit mnemonic description 7 - 0 - watchdog control value 76543210 -----wto2wto1wto0 bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is indeterminate. do not set these bits. 2 - 0 wto2:0 watchdog timer time-out selection bits refer to table 4 for time-out periods.
64 at8xc51snd1c 4109h?8051?01/05 14. mp3 decoder the at8xc51snd1c implement a mpeg i/ii audio layer 3 decoder better known as mp3 decoder. in mpeg i (iso 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 khz. among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining cd audio quality. for example, 3 minutes of cd audio (16-bit pcm, 44.1 khz) data, which needs about 32m bytes of storage, can be encoded into only 2.7m bytes of mpeg i audio layer 3 data. in mpeg ii (iso 13818-3), three additional sampling frequencies: 24, 22.05, and 16 khz are supported for low bit rates applications. the at8xc51snd1c can decode in real-time the mpeg i audio layer 3 encoded data into a pcm audio data, and also supports mpeg ii audio layer 3 additional frequencies. additional features are supported by the at8xc51snd1c mp3 decoder such as volume control, bass, medium, and treble controls, bass boost effect and ancillary data extraction. 14.1 decoder 14.1.1 description the c51 core interfaces to the mp3 decoder through nine special function registers: mp3con, the mp3 control register (see table 12); mp3sta, the mp3 status register (see table 13); mp3dat, the mp3 data register (see table 14); mp3anc, the ancillary data register (see table 16); mp3vol and mp3vor, the mp3 volume left and right control registers (see table 17 and table 18); mp3bas, mp3med, and mp3tre, the mp3 bass, medium, and treble control registers (see table 19, table 20, and table 21); and mpclk, the mp3 clock divider register (see table 22). figure 44 shows the mp3 decoder block diagram. figure 44. mp3 decoder block diagram mpen mp3con.7 mp3 clock audio data from c51 1k bytes 8 mpxreq mp3sta1.n header checker stereo processor huffman decoder imdct side information errxxx mp3sta.5:3 16 sub-band synthesis decoded data to audio interfac e anti-aliasing mpfs1:0 mp3sta.2:1 dequantizer mpver mp3sta.0 mpbbst mp3con.6 mp3vol mp3vor mp3bas mp3med mp3tre ancillary buffer mp3anc frame buffer mp3dat
65 at8xc51snd1c 4109h?8051?01/05 14.1.2 mp3 data the mp3 decoder does not start any frame decoding before having a complete frame in its input buffer (1) . in order to manage the load of mp3 data in the frame buffer, a hard- ware handshake consisting of data request and data acknowledgment is implemented. each time the mp3 decoder needs mp3 data, it sets the mpreq, mpfreq and mpbreq flags respectively in mp3sta and mp3sta1 registers. mpreq flag can gen- erate an interrupt if enabled as explained in section ?interrupt?. the cpu must then load data in the buffer by writing it through mp 3dat register thus acknowledging the previ- ous request. as shown in figure 45, the mpfreq flag remains set while data (i.e a frame) is requested by the decoder. it is cleared when no more data is requested and set again when new data are requested. mpbreq flag toggles at every byte writing. note: 1. the first request after enable, consists in 1024 bytes of data to fill in the input buffer. figure 45. data timing diagram 14.1.3 mp3 clock the mp3 decoder clock is generated by division of the pll clock. the division factor is given by mpcd4:0 bits in mp3clk register. figure 46 shows the mp3 decoder clock generator and its calculation formula. the mp3 decoder clock frequency depends only on the incoming mp3 frames. figure 46. mp3 clock generator and symbol as soon as the frame header has been decoded and the mpeg version extracted, the minimum mp3 input frequency must be programmed according to table 2. table 2. mp3 clock frequency mpfreq flag mpbreq flag mpreq flag cleared when reading mp3sta write to mp3dat mpeg version minimum mp3 clock (mhz) i21 ii 10.5 mpcd4:0 mp3clk mp3 decoder clock mp3clk pllclk mpcd 1 + ---------------------------- = mp3 clock mp3 clock symbol pll clock
66 at8xc51snd1c 4109h?8051?01/05 14.3 audio controls 14.3.1 volume control the mp3 decoder implements volume control on both right and left channels. the mp3vor and mp3vol registers allow a 32-step volume control according to table 4. table 4. volume control 14.4.1 equalization control sound can be adjusted using a 3-band equalizer: a bass band under 750 hz, a medium band from 750 hz to 3300 hz and a treble band over 3300 hz. the mp3bas, mp3med, and mp3tre registers allow a 32-step gain control in each band according to table 5. table 5. bass, medium, treble control 14.5.1 special effect the mpbbst bit in mp3con register allows enabling of a bass boost effect with the fol- lowing characteristics: gain increase of +9 db in the frequency under 375 hz. 14.6 decoding errors the three different errors that can appear during frame processing are detailed in the following sections. all these errors can trigger an interrupt as explained in section "inter- rupt", page 68. 14.6.1 layer error the errsyn flag in mp3sta is set when a non-supported layer is decoded in the header of the frame that has been sent to the decoder. 14.6.2 synchronization error the errsyn flag in mp3sta is set when no synchronization pattern is found in the data that have been sent to the decoder. 14.6.3 crc error when the crc of a frame does not match the one calculated, the flag errcrc in mp3sta is set. in this case, depending on the crcen bit in mp3con, the frame is played or rejected. in both cases, noise may appear at audio output. vol4:0 or vor4:0 volume gain (db) 00000 mute 00001 -33 00010 -27 11110 -1.5 11111 0 bas4:0 or med4:0 or tre4:0 gain (db) 00000 - 00001 -14 00010 -10 11110 +1 11111 +1.5
67 at8xc51snd1c 4109h?8051?01/05 14.7 frame information the mp3 frame header contains information on the audio data contained in the frame. these informations is made available in the mp3sta register for you information. mpver and mpfs1:0 bits allow decodi ng of the sampling frequency according to table 8. mpver bit gives the mpeg version (2 or 1). table 8. mp3 frame frequency sampling 14.9 ancillary data mp3 frames also contain data bits called ancillary data. these data are made available in the mp3anc register for each frame. as shown in figure 47, the ancillary data are available by bytes when mpa nc flag in mp3sta register is set. mpanc flag is set when the ancillary buffer is not empty (at least one ancillary data is available) and is cleared only when there is no more ancillary data in the buffer. this flag can generate an interrupt as explained in section "interrupt", page 68. when set, software must read all bytes to empty the ancillary buffer. figure 47. ancillary data block diagram mpver mpfs1 mpfs0 fs (khz) 0 0 0 22.05 (mpeg ii) 0 0 1 24 (mpeg ii) 0 1 0 16 (mpeg ii) 0 1 1 reserved 1 0 0 44.1 (mpeg i) 1 0 1 48 (mpeg i) 1 1 0 32 (mpeg i) 1 1 1 reserved ancillary data to c51 8 mp3anc 8 mpanc mp3sta.7 7-byte ancillary buffer
68 at8xc51snd1c 4109h?8051?01/05 14.10 interrupt 14.10.1 description as shown in figure 48, the mp3 decoder implements five interrupt sources reported in errcrc, errsyn, errlay, mpreq, and mpanc flags in mp3sta register. all these sources are maskable separately using mskcrc, msksyn, msklay, mskreq, and mskanc mask bits respectively in mp3con register. the mp3 interrupt is enabled by setting emp3 bit in ien0 register. this assumes inter- rupts are globally enabled by setting ea bit in ien0 register. all interrupt flags but mpreq and mpanc are cleared when reading mp3sta register. the mpreq flag is cleared by hardware when no more data is requested (see figure 45) and mpanc flag is cleared by hardware when the ancillary buffer becomes empty. figure 48. mp3 decoder interrupt system 14.10.2 management reading the mp3sta register automatically clears the interrupt flags (acknowledgment) except the mpreq and mpanc flags. this implies that register content must be saved and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts. mp3 decoder interrupt reques t mpanc mp3sta.7 msklay mp3con.2 emp3 ien0.5 mskanc mp3con.4 mskreq mp3con.3 errsyn mp3sta.4 mskcrc mp3con.0 msksyn mp3con.1 mpreq mp3sta.6 e rrcrc mp3sta.3 errlay mp3sta.5
69 at8xc51snd1c 4109h?8051?01/05 figure 49. mp3 interrupt service routine flow note: 1. test these bits only if needed (unmasked interrupt). data request? mpfreq = 1? layer error handler crc error handler data request handler ancillary data handler synchro error handler mp3 decoder isr read mp3sta write mp3 data to mp3dat read ann2:0 ancillary bytes from mp3anc reload mp3 frame through mp3dat load new mp3 frame through mp3dat ancillary data? (1) mpanc = 1? sync error? (1) errsyn = 1? layer error? (1) errsyn = 1?
70 at8xc51snd1c 4109h?8051?01/05 14.11 registers table 12. mp3con register mp3con (s:aah) ? mp3 decoder control register reset value = 0011 1111b 76543210 mpen mpbbst crcen mskanc mskreq msklay msksyn mskcrc bit number bit mnemonic description 7mpen mp3 decoder enable bit set to enable the mp3 decoder. clear to disable the mp3 decoder. 6 mpbbst bass boost bit set to enable the bass boost sound effect. clear to disable the bass boost sound effect. 5 crcen crc check enable bit set to enable processing of frame that contains crc error. frame is played whatever the error. clear to disable processing of frame that contains crc error. frame is skipped. 4 mskanc mpanc flag mask bit set to prevent the mpanc flag from generating a mp3 interrupt. clear to allow the mpanc flag to generate a mp3 interrupt. 3mskreq mpreq flag mask bit set to prevent the mpreq flag from generating a mp3 interrupt. clear to allow the mpreq flag to generate a mp3 interrupt. 2msklay errlay flag mask bit set to prevent the errlay flag from generating a mp3 interrupt. clear to allow the errlay flag to generate a mp3 interrupt. 1 msksyn errsyn flag mask bit set to prevent the errsyn flag from generating a mp3 interrupt. clear to allow the errsyn flag to generate a mp3 interrupt. 0 mskcrc errcrc flag mask bit set to prevent the errcrc flag from generating a mp3 interrupt. clear to allow the errcrc flag to generate a mp3 interrupt.
71 at8xc51snd1c 4109h?8051?01/05 table 13. mp3sta register mp3sta (s:c8h read only) ? mp3 decoder status register reset value = 0000 0001b table 14. mp3dat register mp3dat (s:ach) ? mp3 data register reset value = 0000 0000b 76543210 mpanc mpreq errlay errsyn errcrc mpfs1 mpfs0 mpver bit number bit mnemonic description 7mpanc ancillary data available flag set by hardware as soon as one ancillary data is available (buffer not empty). cleared by hardware when no more ancillary data is available (buffer empty). 6mpreq mp3 data request flag set by hardware when mp3 decoder request data. cleared when reading mp3sta. 5 errlay invalid layer error flag set by hardware when an invalid layer is encountered. cleared when reading mp3sta. 4 errsyn frame synchronization error flag set by hardware when no synchronizati on pattern is encountered in a frame. cleared when reading mp3sta. 3 errcrc crc error flag set by hardware when a frame handling crc is corrupted. cleared when reading mp3sta. 2 - 1 mpfs1:0 frequency sampling bits refer to table 8 for bits description. 0 mpver mpeg version bit set by the mp3 decoder when the loaded frame is a mpeg i frame. cleared by the mp3 decoder when the loaded frame is a mpeg ii frame. 76543210 mpd7 mpd6 mpd5 mpd4 mpd3 mpd2 mpd1 mpd0 bit number bit mnemonic description 7 - 0 mpd7:0 input stream data buffer 8-bit mp3 stream data input buffer.
72 at8xc51snd1c 4109h?8051?01/05 table 15. mp3sta1 register mp3sta1 (s:afh) ? mp3 decoder status register 1 reset value = 0001 0001b table 16. mp3anc register mp3anc (s:adh read only) ? mp3 ancillary data register reset value = 0000 0000b table 17. mp3vol register mp3vol (s:9eh) ? mp3 volume left control register reset value = 0000 0000b 76543210 - - - mpfreq mp f req--- bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4mpfreq mp3 frame data request flag set by hardware when mp3 decoder request data. cleared when mp3 decoder no more request data . 3mpbreq mp3 byte data request flag set by hardware when mp3 decoder request data. cleared when writing to mp3dat. 2 - 0 - reserved the value read from these bits is always 0. do not set these bits. 76543210 and7 and6 and5 and4 and3 and2 and1 and0 bit number bit mnemonic description 7 - 0 and7:0 ancillary data buffer mp3 ancillary data byte buffer. 76543210 - - - vol4 vol3 vol2 vol1 vol0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 vol4:0 volume left value refer to table 4 for the left channel volume control description.
73 at8xc51snd1c 4109h?8051?01/05 table 18. mp3vor register mp3vor (s:9fh) ? mp3 volume right control register reset value = 0000 0000b table 19. mp3bas register mp3bas (s:b4h) ? mp3 bass control register reset value = 0000 0000b table 20. mp3med register mp3med (s:b5h) ? mp3 medium control register reset value = 0000 0000b 76543210 - - - vor4 vor3 vor2 vor1 vor0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 vor4:0 volume right value refer to table 4 for the right channel volume control description. 76543210 - - - bas4 bas3 bas2 bas1 bas0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 bas4:0 bass gain value refer to table 5 for the bass control description. 76543210 - - med5 med4 med3 med2 med1 med0 bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not set these bits. 5-0 med5:0 medium gain value refer to table 5 for the medium control description.
74 at8xc51snd1c 4109h?8051?01/05 table 21. mp3tre register mp3tre (s:b6h) ? mp3 treble control register reset value = 0000 0000b table 22. mp3clk register mp3clk (s:ebh) ? mp3 clock divider register reset value = 0000 0000b 76543210 - - tre5 tre4 tre3 tre2 tre1 tre0 bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not set these bits. 5-0 tre5:0 treble gain value refer to table 5 for the treble control description. 76543210 - - - mpcd4 mpcd3 mpcd2 mpcd1 mpcd0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 mpcd4:0 mp3 decoder clock divider 5-bit divider for mp3 decoder clock generation.
75 at8xc51snd1c 4109h?8051?01/05 15. audio output interface the at8xc51snd1c implement an audio output interface allowing the audio bitstream to be output in various formats. it is compatible with right and left justification pcm and i 2 s formats and thanks to the on-chip pll (see section ?clock controller?, page 12) allows connection of almost all of the co mmercial audio dac families available on the market. the audio bitstream can be from 2 different types: the mp3 decoded bitstream coming from the mp3 decoder for playing songs. the audio bitstream coming from the mcu for outputting voice or sounds. 15.1 description the c51 core interfaces to the audio interface through five special function registers: audcon0 and audcon1, the audio control registers (see table 11 and table 12); audsta, the audio status register (see table 13); auddat, the audio data register (see table 14); and audclk, the audio cl ock divider register (see table 15). figure 50 shows the audio interface block diagram, blocks are detailed in the following sections. figure 50. audio interface block diagram aud clock udrn audsta.6 0 1 dsiz audcon0.1 dsel clock generator dclk dou t sclk just4:0 audcon0.7:3 pol audcon0.2 auden audcon1.0 hlr audcon0.0 0 1 src audcon1.7 8 data converter audio data from c51 audio data from mp3 dup1:0 audcon1.2:1 16 16 sreq audsta.7 audio buffer aubusy audsta.5 data ready drqen audcon1.6 mp3 buffer decoder 16 sample request to mp3 decoder auddat
76 at8xc51snd1c 4109h?8051?01/05 15.2 clock generator the audio interface clock is generated by division of the pll clock. the division factor is given by aucd4:0 bits in clkaud register . figure 51 shows the audio interface clock generator and its calculation formula. the audio interface clock frequency depends on the incoming mp3 frames and the audio dac used. figure 51. audio clock generator and symbol as soon as audio interface is enabled by setting auden bit in audcon1 register, the master clock generated by the pll is output on the sclk pin which is the dac system clock. this clock is output at 256 or 384 times the sampling frequency depending on the dac capabilities. hlr bit in audcon0 register must be set according to this rate for properly generating the audio bit clock on the dclk pin and the word selection clock on the dsel pin. these clocks are not generated when no data is available at the data converter input. for dac compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits per channel using the dsiz bit in audcon0 register (see section "data con- verter", page 76), and the word selection signal is programmable for outputting left channel on low or high level according to pol bit in audcon0 register as shown in figure 52. figure 52. dsel output polarity 15.3 data converter the data converter block converts the audio stream input from the 16-bit parallel format to a serial format. for accepting all pcm formats and i 2 s format, just4:0 bits in audcon0 register are used to shift the data output point. as shown in figure 53, these bits allow msb justification by setting ju st4:0 = 00000, lsb justification by setting just4:0 = 10000, i 2 s justification by setting just4:0 = 00001, and more than 16-bit lsb justification by filling the low significant bits with logic 0. aucd4:0 audclk audio interface clock audclk pllclk au c d1 + --------------------------- = audio clock symbol aud clock pll clock left channel right channel pol = 1 pol = 0 left channel right channel
77 at8xc51snd1c 4109h?8051?01/05 figure 53. audio output format the data converter receives its audio stream from 2 sources selected by the src bit in audcon1 register. when cleared, the audio stream comes from the mp3 decoder (see section ?mp3 decoder?, page 64) for song playing. when set, the audio stream is com- ing from the c51 core for voice or sound playing. as soon as first audio data is input to the data converter, it enables the clock generator for generating the bit and word clocks. 15.4 audio buffer in voice or sound playing mode, the audio stream comes from the c51 core through an audio buffer. the data is in 8-bit format and is sampled at 8 khz. the audio buffer adapts the sample format and rate. the sample format is extended to 16 bits by filling the lsb to 00h. rate is adapted to the dac rate by duplicating the data using dup1:0 bits in audcon1 register according to table 5. the audio buffer interfaces to the c51 core through three flags: the sample request flag (sreq in audsta register), the under-run flag (undr in audsta register) and the busy flag (aubusy in audsta register). sreq and undr can generate an interrupt request as explained in section "interrupt request", page 78. the buffer size is 8 bytes large. sreq is set when the samples number switches from 4 to 3 and reset when the samples number switches from 4 to 5; undr is set when the buffer becomes empty sig- naling that the audio interface ran out of samples; and aubusy is set when the buffer is full. dsel dclk dout msb i 2 s format with dsiz = 0 and just4:0 = 00001. lsb b14 msb lsb b14 b1 b1 dsel dclk dout msb i 2 s format with dsiz = 1 and just4:0 = 00001. lsb b14 msb lsb b14 1 2 3 13 14 15 16 1 2 3 13 14 15 16 left channel right channel 1 2 3 17 18 32 1 2 3 17 18 32 dsel dclk dout b14 msb/lsb justified format with dsiz = 0 and just4:0 = 00000. msb b1 b15 msb b1 lsb lsb 1 2 3 13 14 15 16 1 2 3 13 14 15 16 left channel right channel left channel right channel dsel dclk dout 16-bit lsb justified format with dsiz = 1 and just4:0 = 10000. 11618 32 32 left channel right channel 17 31 msb b14 lsb b1 msb b14 lsb b1 11618 17 31 dsel dclk dout 18-bit lsb justified format with dsiz = 1 and just4:0 = 01110. 115 3032 left channel right channel 16 31 msb b16 b2 1 b1 lsb msb b16 b2 b1 lsb 15 30 32 16 31
78 at8xc51snd1c 4109h?8051?01/05 table 5. sample duplication factor 15.6 mp3 buffer in song playing mode, the audio stream comes from the mp3 decoder through a buffer. the mp3 buffer is used to store the decoded mp3 data and interfaces to the decoder through a 16-bit data input and data request signal. this signal asks for data when the buffer has enough space to receive new data. data request is conditioned by the dreqen bit in audcon1 register. when set, the buffer requests data to the mp3 decoder. when cleared no more data is requested but data are output until the buffer is empty. this bit can be used to suspend the audio generation (pause mode). 15.7 interrupt request the audio interrupt request can be generated by 2 sources when in c51 audio mode: a sample request when sreq flag in audsta register is set to logic 1, and an under-run condition when udrn flag in audsta register is set to logic 1. both sources can be enabled separately by masking one of them using the msreq and mudrn bits in audcon1 register. a global enable of the audi o interface is provided by setting the eaud bit in ien0 register. the interrupt is requested each time one of the 2 sources is set to one. the source flags are cleared by writing some data in the audio buffer through auddat, but the global audio interrupt flag is cleared by hardware when the interrupt service routine is executed. figure 54. audio interface interrupt system 15.8 mp3 song playing in mp3 song playing mode, the operations to do are to configure the pll and the audio interface according to the dac selected. the audio clock is programmed to generate the 256fs or 384fs as explained in section "clock generator", page 76. figure 55 shows the configuration flow of the audio interface when in mp3 song mode. dup1 dup0 factor 0 0 no sample duplication, dac rate = 8 khz (c51 rate). 0 1 one sample duplication, dac rate = 16 khz (2 x c51 rate). 1 0 2 samples duplication, dac rate = 32 khz (4 x c51 rate). 1 1 three samples duplication, dac rate = 48 khz (6 x c51 rate). sreq audsta.7 audio interrup t reques t udrn audsta.6 msreq audcon1.5 eaud ien0.6 mudrn audcon1.4
79 at8xc51snd1c 4109h?8051?01/05 figure 55. mp3 mode audio configuration flow 15.9 voice or sound playing in voice or sound playing mode, the operations required are to configure the pll and the audio interface according to the dac selected. the audio clock is programmed to generate the 256fs or 384fs as for the mp3 playing mode. the data flow sent by the c51 is then regulated by interrupt and data is loaded 4 bytes by 4 bytes. figure 56 shows the configuration flow of the audio interface when in voice or sound mode. figure 56. voice or sound mode audio flows note: 1. an under-run occurrence signifies that c51 core did not respond to the previous sample request interrupt. it may never occur for a correct voice/sound generation. it is the user?s responsibility to mask it or not. mp3 mode configuration configure interface hlr = x dsiz = x pol = x just4:0 = xxxxxb src = 0 program audio clock enable dac system clock auden = 1 wait for dac set-up time enable data request drqen = 1 select audio src = 1 voice/song mode configuration configure interface hlr = x dsiz = x pol = x just4:0 = xxxxxb dup1:0 = xx program audio clock enable dac system clock auden = 1 wait for dac enable time load 8 samples in the audio buffer enable interrupt set msreq & mudrn 1 eaud = 1 audio interrupt service routine under-run condition 1 load 4 samples in the audio buffer sample request? sreq = 1?
80 at8xc51snd1c 4109h?8051?01/05 15.10 registers table 11. audcon0 register audcon0 (s:9ah) ? audio interface control register 0 reset value = 0000 1000b table 12. audcon1 register audcon1 (s:9bh) ? audio interface control register 1 reset value = 1011 0010b 76543210 just4 just3 just2 just1 just0 pol dsiz hlr bit number bit mnemonic description 7 - 3 just4:0 audio stream justification bits refer to section "data converter", page 76 for bits description. 2pol dsel signal output polarity set to output the left channel on high level of dsel output (pcm mode). clear to output the left channel on the low level of dsel output (i 2 s mode). 1dsiz audio data size set to select 32-bit data output format. clear to select 16-bit data output format. 0hlr high/low rate bit set by software when the pll clock frequency is 384fs. clear by software when the pll clock frequency is 256fs. 76543210 src drqen msreq mudrn - dup1 dup0 auden bit number bit mnemonic description 7src audio source bit set to select c51 as audio source for voice or sound playing. clear to select the mp3 decoder output as audio source for song playing. 6 drqen mp3 decoded data request enable bit set to enable data request to the mp3 decoder and to start playing song. clear to disable data request to the mp3 decoder. 5msreq audio sample request flag mask bit set to prevent the sreq flag from generating an audio interrupt. clear to allow the sreq flag to generate an audio interrupt. 4 mudrn audio sample under-run flag mask bit set to prevent the udrn flag from generating an audio interrupt. clear to allow the udrn flag to generate an audio interrupt. 3- reserved the value read from this bit is always 0. do not set this bit. 2 - 1 dup1:0 audio duplication factor refer to table 5 for bits description. 0 auden audio interface enable bit set to enable the audio interface. clear to disable the audio interface.
81 at8xc51snd1c 4109h?8051?01/05 table 13. audsta register audsta (s:9ch read only) ? audio interface status register reset value = 1100 0000b table 14. auddat register auddat (s:9dh) ? audio interface data register reset value = 1111 1111b table 15. audclk register audclk (s:ech) ? audio clock divider register reset value = 0000 0000b 76543210 sreq udrn aubusy ----- bit number bit mnemonic description 7sreq audio sample request flag set in c51 audio source mode when the audio interface request samples (buffer half empty). this bit generates an interrupt if not masked and if enabled in ien0. cleared by hardware when samples are loaded in auddat. 6 udrn audio sample under-run flag set in c51 audio source mode when the audio interface runs out of samples (buffer empty). this bit generates an interrupt if not masked and if enabled in ien0. cleared by hardware when samples are loaded in auddat. 5 aubusy audio interface busy bit set in c51 audio source mode when the audio interface can not accept more sample (buffer full). cleared by hardware when buffer is no more full. 4 - 0 - reserved the value read from these bits is always 0. do not set these bits. 76543210 aud7 aud6 aud5 aud4 aud3 aud2 aud1 aud0 bit number bit mnemonic description 7 - 0 aud7:0 audio data 8-bit sampling data for voice or sound playing. 76543210 - - - aucd4 aucd3 aucd2 aucd1 aucd0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 aucd4:0 audio clock divider 5-bit divider for audio clock generation.
82 at8xc51snd1c 4109h?8051?01/05 16. universal serial bus the at8xc51snd1c implements a usb device controller supporting full speed data transfer. in addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: endpoint 0: 32-byte fifo, default control endpoint endpoint 1, 2: 64-byte ping-pong fifo, this allows the firmware to be developed co nforming to most usb device classes, for example: usb mass storage class bulk-only transport, revision 1.0 - september 31, 1999 usb human interface device class, version 1.1 - april 7, 1999 usb device firmware upgrade class, revision 1.0 - may 13, 1999 16.0.1 usb mass storage class bulk-only transport within the bulk-only framework, the control endpoint is only used to transport class- specific and standard usb requests for devic e set-up and configuration. one bulk-out endpoint is used to transport commands and data from the host to the device. one bulk in endpoint is used to transport status and data from the device to the host. the following at8xc51snd1c configuration adheres to those requirements: endpoint 0: 32 bytes, control in-out endpoint 1: 64 bytes, bulk-in endpoint 2: 64 bytes, bulk-out 16.0.2 usb device firmware upgrade (dfu) the usb device firmware update (dfu) protocol can be used to upgrade the on-chip flash memory of the at89c51snd1c. this allows installing product enhancements and patches to devices that are already in the field. 2 different configurations and descriptor sets are used to support dfu functions. the run-time configuration co-exist with the usual functions of the device, which is usb mass storage for at89c51snd1c. it is used to initiate dfu from the normal operating mode. the dfu configuration is used to perform the firmware update after device re-configuration and usb reset. it excludes any other function. only the default control pipe (endpoint 0) is used to support dfu services in both configurations. the only possible value for the maxpacketsize in the dfu configuration is 32 bytes, which is the size of the fifo implemented for endpoint 0.
83 at8xc51snd1c 4109h?8051?01/05 16.1 description the usb device controller provides the hardware that the at8xc51snd1c needs to interface a usb link to a data flow stored in a double port memory. it requires a 48 mhz reference clock provided by the clock controller as detailed in sec- tion "clock controller", page 83. this clock is used to generate a 12 mhz full speed bit clock from the received usb differential data flow and to transmit data according to full speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block. the serial interface engine (sie) block performs nrzi encoding and decoding, bit stuff- ing, crc generation and checking, and the serial-parallel data conversion. the universal function interface (ufi) controls the interface between the data flow and the dual port ram, but also the interface with the c51 core itself. figure 59 shows how to connect the at8xc51snd1c to the usb connector. d+ and d- pins are connected through 2 termination resistors. value of these resistors is detailed in the section ?dc characteristics?. figure 57. usb device controller block diagram figure 58. usb connection 16.1.1 clock controller the usb controller clock is generated by division of the pll clock. the division factor is given by usbcd1:0 bits in usbclk register (see table 24). figure 59 shows the usb controller clock generator and its calculation formula. the usb controller clock fre- quency must always be 48 mhz. usb clock 48 mhz 12 mhz d+ d- dpll sie ufi usb buffer to/from c51 cor e d+ d- r usb vbus r usb gnd d+ d- vss to power supply
84 at8xc51snd1c 4109h?8051?01/05 figure 59. usb clock generator and symbol 16.1.2 serial interface engine (sie) the sie performs the following functions: nrzi data encoding and decoding. bit stuffing and unstuffing. crc generation and checking. acks and nacks automatic generation. token type identifying. address checking. clock recovery (using dpll). figure 60. sie block diagram usbcd1:0 usbclk 48 mhz usb clock usbclk pllclk usbcd 1 + -------------------------------- = usb clock usb clock symbol pll clock 8 start of packet detector clock recover sync detector pid decoder address decoder serial to parallel converter crc5 & crc16 generator/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ? nrz bit unstuffing packet bit counter end of packet detector usb clock 48 mhz sysclk data in d+ d- (12 mhz) 8 data ou t
85 at8xc51snd1c 4109h?8051?01/05 16.1.3 function interface unit (ufi) the function interface unit provides the interface between the at8xc51snd1c and the sie. it manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint fifos. figure 62 shows typical usb in and out transactions reporting the split in the hard- ware (ufi) and software (c51) load. figure 61. ufi block diagram figure 62. usb typical transaction load to/from c51 cor e endpoint control c51 side endpoint control usb side endpoint 2 endpoint 1 endpoint 0 usbcon usbint usbien uepint uepien uepnum uepstax usbaddr uepconx uepdatx ueprst ubyctx ufnumh ufnuml asynchronous information transfer control fsm to/from sie 1 2 mhz dpll out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack c51 interrupt in data1 c51 interrupt endpoint fifo writ e
86 at8xc51snd1c 4109h?8051?01/05 16.2 configuration 16.2.1 general configuration usb controller enable before any usb transaction, the 48 mhz required by the usb controller must be correctly generated (see ?clock controller? on page 19). the usb controller should be then enabled by setting the eusb bit in the usbcon register. set address after a reset or a usb reset, the software has to set the fen (function enable) bit in the usbaddr register. this action will allow the usb controller to answer to the requests sent at the address 0. when a set_address request has been received, the usb controller must only answer to the address defined by the request. the new address should be stored in the usbaddr register. the fen bit and the fadden bit in the usbcon register should be set to allow the usb controller to answer only to requests sent at the new address. set configuration the confg bit in the usbcon register should be set after a set_configuration request with a non-ze ro value. otherwise, this bit should be cleared. 16.2.2 endpoint configuration selection of an endpoint the endpoint register access is performed using the uepnum register. the registers ?uepstax ? uepconx ?uepdatx ?ubyctx theses registers correspond to the endpoint whose number is stored in the uep- num register. to select an endpoint, the firmware has to write the endpoint number in the uepnum register. figure 63. endpoint selection uepnum endpoint 0 endpoint 2 uepsta0 uepcon0 uepdat0 uepsta2 uepcon2 uepdat2 0 1 2 sfr registers uepstax uepconx uepdatx x ubyct0 ubyct2 ubyctx
87 at8xc51snd1c 4109h?8051?01/05 endpoint enable before using an endpoint, this must be enabled by setting the epen bit in the uep- conx register. an endpoint which is not enabled won?t answer to any usb request. the default control endpoint (endpoint 0) should always be enabled in order to answer to usb standard requests. endpoint type configuration all standard endpoints can be configured in control, bulk, interrupt or isochronous mode. the ping-pong endpoints can be configured in bulk, interrupt or isochronous mode. the configuration of an endpoint is performed by setting the field eptype with the following values: ? control: eptype = 00b ? isochronous: eptype = 01b ? bulk: eptype = 10b ? interrupt: eptype = 11b the endpoint 0 is the default control endpoint and should always be configured in control type. endpoint direction configuration for bulk, interrupt and isochronous endpoints, the direction is defined with the epdir bit of the uepconx register with the following values: ? in: epdir = 1b ? out: epdir = 0b for control endpoints, the epdir bit has no effect. summary of endpoint configuration: do not forget to select the correct endpoint number in the uepnum register before accessing endpoint specific registers. table 3. summary of endpoint configuration endpoint configuration epen epdir eptype uepconx disabled 0b xb xxb 0xxx xxxb control 1b xb 00b 80h bulk-in 1b 1b 10b 86h bulk-out 1b 0b 10b 82h interrupt-in 1b 1b 11b 87h interrupt-out 1b 0b 11b 83h isochronous-in 1b 1b 01b 85h isochronous-out 1b 0b 01b 81h
88 at8xc51snd1c 4109h?8051?01/05 endpoint fifo reset before using an endpoint, its fifo should be reset. this action resets the fifo pointer to its original value, resets the byte counter of the endpoint (ubyctx regis- ter), and resets the data toggle bit (dtgl bit in uepconx). the reset of an endpoint fifo is performed by setting to 1 and resetting to 0 the corresponding bit in the ueprst register. for example, in order to reset the endpoint number 2 fifo, write 0000 0100b then 0000 0000b in the ueprst register. note that the endpoint reset doesn?t reset the bank number for ping-pong endpoints. 16.4 read/write data fifo 16.4.1 read data fifo the read access for each out endpoint is performed using the uepdatx register. after a new valid packet has been received on an endpoint, the data are stored into the fifo and the byte counter of the endpoint is updated (ubyctx registers). the firmware has to store the endpoint byte counter before any access to the endpoint fifo. the byte counter is not updated when reading the fifo. to read data from an endpoint, select the correct endpoint number in uepnum and read the uepdatx register. this action automatically decreases the corresponding address vector, and the next data is then available in the uepdatx register. 16.4.2 write data fifo the write access for each in endpoint is performed using the uepdatx register. to write a byte into an in endpoint fifo, select the correct endpoint number in uep- num and write into the uepdatx register. the corresponding address vector is automatically increased, and another write can be carried out. warning 1: the byte counter is not updated. warning 2: do not write more bytes than supported by the corresponding endpoint. 16.4.3 fifo mapping figure 64. endpoint fifo configuration uepnum endpoint 0 endpoint 2 uepsta0 uepcon0 uepdat0 uepsta2 uepcon2 uepdat2 0 1 2 sfr registers uepstax uepconx uepdatx x ubyct0 ubyct2 ubyctx
89 at8xc51snd1c 4109h?8051?01/05 16.5 bulk/interrupt transactions bulk and interrupt transactions are managed in the same way. 16.5.1 bulk/interrupt out transactions in standard mode figure 65. bulk/interrupt out transactions in standard mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on an endpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to accept the next out packet on this end- point. until the rxoutb0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests. if the host sends more bytes than support ed by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that the packet is valid if the crc is correct and the endpoint byte counter contains the number of bytes sent by the host. out data0 (n bytes) ack host ufi c51 endpoint fifo read byte 1 out data1 nak rxoutb0 endpoint fifo read byte 2 endpoint fifo read byte n clear rxoutb0 out data1 nak out data1 ack rxoutb0 endpoint fifo read byte 1
90 at8xc51snd1c 4109h?8051?01/05 16.5.2 bulk/interrupt out transactions in ping-pong mode figure 66. bulk/interrupt out transactions in ping-pong mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyctx regis- ter. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to accept the next out packet on the endpoint bank 0. this action switches the endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests on the bank 0 endpoint fifo. when a new valid out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests on the bank 1 endpoint fifo. the rxoutb0 and rxoutb1 bits are, alternatively, set by the usb controller at each new valid packet receipt. the firmware has to clear one of these 2 bits after having read all the data fifo to allow a new valid packet to be stored in the corresponding bank. a nak handshake is sent by the usb controller only if the banks 0 and 1 has not been released by the firmware. out data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - read byte 1 rxoutb0 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte n clear rxoutb0 out data1 (m bytes) ack rxoutb1 endpoint fifo bank 1 - read byte 1 endpoint fifo bank 1 - read byte 2 endpoint fifo bank 1 - read byte m clear rxoutb1 out data0 (p bytes) ack rxoutb0 endpoint fifo bank 0 - read byte 1 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte p clear rxoutb0
91 at8xc51snd1c 4109h?8051?01/05 if the host sends more bytes than support ed by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that the packet is valid if the crc is correct. 16.5.3 bulk/interrupt in transactions in standard mode figure 67. bulk/interrupt in transactions in standard mode an endpoint should be first enabled and configured before being able to send bulk or interrupt packets. the firmware should fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning this endpoint. to send a zero length packet, the firmware should set the txrdy bit without writing any data into the endpoint fifo. until the txrdy bit has been set by the firmware, the usb controller will answer a nak handshake for each in requests. to cancel the sending of this packet, the firmware has to reset the txrdy bit. the packet stored in the endpoint fifo is then cleared and a new packet can be written and sent. when the in packet has been sent and acknowledged by the host, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo with new data. the firmware should never write more bytes than supported by the endpoint fifo. all usb retry mechanisms are automatically managed by the usb controller. in data0 (n bytes) ack host ufi c51 endpoint fifo write byte 1 in nak txcmpl endpoint fifo write byte 2 endpoint fifo write byte n set txrdy clear txcmpl endpoint fifo write byte 1
92 at8xc51snd1c 4109h?8051?01/05 16.5.4 bulk/interrupt in transactions in ping-pong mode figure 68. bulk/interrupt in transactions in ping-pong mode an endpoint should be first enabled and configured before being able to send bulk or interrupt packets. the firmware should fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning the endpoint. the fifo banks are automatically switched, and the firmware can immediately write into the endpoint fifo bank 1. when the in packet concerning the bank 0 has been sent and acknowledged by the host, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the tx cmpl bit before filling the endpoint fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been sent and acknowledged by the host, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the tx cmpl bit before filling the endpoint fifo bank 1 with new data. the bank switch is performed by the usb controller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller will answer a nak handshake for each in requests concerning this bank. note that in the example above, the firmware clears the transmit complete bit (txcbulk-outmpl) before setting the transmit ready bit (txrdy). this is done in order to avoid the firmware to clear at the same time the txcmpl bit for for bank 0 and the bank 1. the firmware should never write more bytes than supported by the endpoint fifo. in data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - write byte 1 in nack txcmpl endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte n set txrdy endpoint fifo bank 1 - write byte 1 endpoint fifo bank 1 - write byte 2 endpoint fifo bank 1 - write byte m set txrdy in data1 (m bytes) ack endpoint fifo bank 0 - write byte 1 endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte p set txrdy clear txcmpl in data0 (p bytes) ack txcmpl clear txcmpl endpoint fifo bank 1 - write byte 1
93 at8xc51snd1c 4109h?8051?01/05 16.6 control transactions 16.6.1 setup stage the dir bit in the uepstax register should be at 0. receiving setup packets is the same as receiving bulk out packets, except that the rxsetup bit in the uepstax register is set by the usb controller instead of the rxoutb0 bit to indicate that an out packet with a setup pid has been received on the control endpoint. when the rxsetup bit has been set, all the other bits of the uep- stax register are cleared and an interrupt is triggered if enabled. the firmware has to read the setup request stored in the control endpoint fifo before clearing the rxsetup bit to free the endpoint fifo for the next transaction. 16.6.2 data stage: control endpoint direction the data stage management is similar to bulk management. a control endpoint is managed by the usb controller as a full-duplex endpoint: in and out. all other endpoint types are managed as half-duplex endpoint: in or out. the firmware has to specify the control endpoint direction for the data stage using the dir bit in the uepstax register. if the data stage consists of ins, the firmware has to set the dir bit in the uepstax register before writing into the fifo and sending the data by setting to 1 the txrdy bit in the uepstax register. the in transaction is complete when the txcmpl has been set by the hardware. the firmware should clear the txcmpl bit before any other transaction. if the data stage consists of outs, the firmware has to leave the dir bit at 0. the rxoutb0 bit is set by hardware when a new valid packet has been received on the endpoint. the firmware must read the data stored into the fifo and then clear the rxoutb0 bit to reset the fifo and to allow the next transaction. to send a stall handshake, see ?stall handshake? on page 96. 16.6.3 status stage the dir bit in the uepstax register should be reset at 0 for in and out status stage. the status stage management is similar to bulk management. for a control write transaction or a no-data control transaction, the status stage consists of a in zero length packet (see ?bulk/interrupt in transactions in standard mode? on page 91). to send a stall handshake, see ?stall handshake? on page 96. for a control read transaction, the status stage consists of a out zero length packet (see ?bulk/interrupt out transactions in standard mode? on page 89).
94 at8xc51snd1c 4109h?8051?01/05 isochronous tr ansactions 16.6.4 isochronous out transactions in standard mode an endpoint should be first enabled and configured before being able to receive isochro- nous packets. when an out packet is received on an endpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corre bulk-outsponding endpoint, store the numbe r of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to store the next out packet data into the endpoint fifo. until the rxoutb0 bit has been cleared by the firmware, the data sent by the host at each out transaction will be lost. if the rxoutb0 bit is cleared while the host is sending data, the usb controller will store only the remaining bytes into the fifo. if the host sends more bytes than support ed by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that the packet is valid if the crc is correct. 16.6.5 isochronous out transactions in ping-pong mode an endpoint should be first enabled and configured before being able to receive isochro- nous packets. when a out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to store the next out packet data into the end- point fifo bank 0. this action switches the endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmware, the data sent by the host on the bank 0 endpoint fifo will be lost. if the rxoutb0 bit is cleared while the host is sending data on the endpoint bank 0, the usb controller will store only the remaining bytes into the fifo. when a new out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmware, the data sent by the host on the bank 1 endpoint fifo will be lost. the rxoutb0 and rxoutb1 bits are alternatively set by the usb controller at each new packet receipt. the firmware has to clear one of these 2 bits after having read all the data fifo to allow a new packet to be stored in the corresponding bank.
95 at8xc51snd1c 4109h?8051?01/05 if the host sends more bytes than support ed by the endpoint fifo, the overflow data won?t be stored, but the usb controller will consider that the packet is valid if the crc is correct. 16.6.6 isochronous in transactions in standard mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning this endpoint. if the txrdy bit is not set when the in request occurs, nothing will be sent by the usb controller. when the in packet has been sent, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo with new data. the firmware should never write more bytes than supported by the endpoint fifo 16.6.7 isochronous in transactions in ping-pong mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning the endpoint. the fifo banks are automatically switched, and the firmware can immediately write into the endpoint fifo bank 1. if the txrdy bit is not set when the in request occurs, nothing will be sent by the usb controller. when the in packet concerning the bank 0 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo bank 1 with new data. the bank switch is performed by the usb controller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller won?t send anything at each in requests concerning this bank. the firmware should never write more bytes than supported by the endpoint fifo.
96 at8xc51snd1c 4109h?8051?01/05 16.7 miscellaneous 16.7.1 usb reset the eorint bit in the usbint register is set by hardware when a end of reset has been detected on the usb bus. this triggers a usb interrupt if enabled. the usb con- troller is still enabled, but all the usb regi sters are reset by hardware. the firmware should clear the eorint bit to allow the next usb reset detection. 16.7.2 stall handshake this function is only available for control, bulk, and interrupt endpoints. the firmware has to set the stallrq bit in the uepstax register to send a stall handshake at the next request of the host on the endpoint selected with the uepnum register. the rxsetup, txrdy, txcmpl, rxoutb0 and rxoutb1 bits must be first resseted to 0. the bit stlcrc is set at 1 by the usb controller when a stall has been sent. this triggers an interrupt if enabled. the firmware should clear the stallrq and stlcrc bits after each stall sent. the stallrq bit is cleared automatically by hardware when a valid setup pid is received on a control type endpoint. important note: when a clear halt feature occurs for an endpoint, the firmware should reset this endpoint using the ueprst resgister in order to reset the data toggle management. 16.7.3 start of frame detection the sofint bit in the usbint register is set when the usb controller detects a start of frame pid. this triggers an interrupt if enabled. the firmware should clear the sofint bit to allow the next start of frame detection. 16.7.4 frame number when receiving a start of frame, the frame number is automatically stored in the ufnuml and ufnumh registers. the crcok and crcerr bits indicate if the crc of the last start of frame is valid (crcok set at 1) or corrupted (crcerr set at 1). the ufnuml and ufnumh registers are automatically updated when receiving a new start of frame. 16.7.5 data toggle bit the data toggle bit is set by hardware when a data0 packet is received and accepted by the usb controller and cleared by hardware when a data1 packet is received and accepted by the usb controller. this bit is reset when the firmware resets the endpoint fifo using the ueprst register. for control endpoints, each setup transaction starts with a data0 and data toggling is then used as for bulk endpoints until the end of the data stage (for a control write transfer). the status stage completes the data transfer with a data1 (for a control read transfer). for isochronous endpoints, the device firmware should ignore the data-toggle.
97 at8xc51snd1c 4109h?8051?01/05 suspend/resume management 16.7.6 suspend the suspend state can be detected by the u sb controller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if enabled. in order to reduce current consumption, the firmware can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mode. the resume detection is still active. the usb pad is put in idle mode when the firmware clear the spint bit. in order to avoid a new suspend detection 3ms later, the firmware has to disable the usb clock input using the suspclk bit in the usbcon register. the usb pad automatically exits of idle mode when a wake-up event is detected. the stop of the 48 mhz clock from the pll should be done in the following order: 1. disable of the 48 mhz clock input of the usb controller by setting to 1 the sus- pclk bit in the usbcon register. 2. disable the pll by clearing the pllen bit in the pllcon register. 16.7.7 resume when the usb controller is in suspend state, the resume detection is active even if all the clocks are disabled and if the c51 is in idle or power-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bus. this triggers an inter- rupt if enabled. this interrupt wakes up the cpu from its idle or power-down state and the interrupt function is then executed. the firmware will first enable the 48 mhz gener- ation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbint register before any other usb operation in order to wake up the usb controller from its suspend mode. the usb controller is then re-activated. figure 69. example of a suspend/resume management usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint
98 at8xc51snd1c 4109h?8051?01/05 16.7.8 upstream resume a usb device can be allowed by the host to send an upstream resume for remote wake-up purpose. when the usb controller receives the set_feature request: device_remote_wakeup, the firmware should set to 1 the rmwupe bit in the usbcon register to enable this functionality. rmwupe value should be 0 in the other cases. if the device is in suspend mode, the usb controller can send an upstream resume by clearing first the spint bit in the usbint register and by setting then to 1 the sdrm- wup bit in the usbcon register. the usb controller sets to 1 the uprsm bit in the usbcon register. all clocks must be enabled first. the remote wake is sent only if the usb bus was in suspend state for at least 5ms. when the upstream resume is com- pleted, the uprsm bit is reset to 0 by hardware. the firmware should then clear the sdrmwup bit. figure 70. example of remote wakeup management usb controller init detection of a suspend state spint set rmwupe suspend management enable clocks upstream resume sent uprsm clear spint set sdmwup clear sdrmwup set_feature: device_remote_wakeup need usb resume uprsm = 1
99 at8xc51snd1c 4109h?8051?01/05 16.8 usb interrupt system 16.8.1 interrupt system priorities figure 71. usb interrupt control system table 1. priority levels 16.8.2 usb interrupt control system as shown in figure 72, many events can produce a usb interrupt: txcmpl: transmitted in data (table 16 on page 105). this bit is set by hardware when the host accept a in packet. rxoutb0: received out data bank 0 (table 16 on page 105). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 0. rxoutb1: received out data bank 1 (only for ping-pong endpoints) (table 16 on page 105). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 1. rxsetup: received setup (table 16 on page 105). this bit is set by hardware when an setup packet is accepted by the endpoint. stlcrc: stalled (only for control, bulk and interrupt endpoints) (table 16 on page 105). this bit is set by hardware when a stall handshake has been sent as requested by stallrq, and is reset by hardware when a setup packet is received. sofint: start of frame interrupt (table 12 on page 102). this bit is set by hardware when a usb start of frame packet has been received. wupcpu: wake-up cpu interrupt (table 12 on page 102). this bit is set by hardware when a usb resume is detected on the usb bus, after a suspend state. spint: suspend interrupt (table 12 on page 102). this bit is set by hardware when a usb suspend is detected on the usb bus. eusb ie1.6 ea ie0.7 usb controller iph/l interrupt enable lowest priority interrupts priority enable 00 01 10 11 d+ d- iphusb iplusb usb priority level 0 0 0..................lowest 01 1 10 2 1 1 3..................highest
100 at8xc51snd1c 4109h?8051?01/05 figure 72. usb interrupt control block diagram txcmp uepstax.0 rxoutb0 uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ie1.6 endpoint x (x = 0..2) eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 rxoutb1 uepstax.6 eeorint usbien.4 nakout uepconx.5 nakin uepconx.4 nakien uepconx.6
101 at8xc51snd1c 4109h?8051?01/05 16.9 registers table 10. usbcon register usbcon (s:bch) ? usb global control register reset value = 0000 0000b 76543210 usbe suspclk sdrmwup - uprsm rmwupe confg fadden bit number bit mnemonic description 7usbe usb enable bit set this bit to enable the usb controller. clear this bit to disable and reset the usb controller, to disable the usb transceiver an to disable the usb controllor clock inputs. 6suspclk suspend usb clock bit set to disable the 48 mhz clock input (resume detection is still active). clear to enable the 48 mhz clock input. 5 sdrmwu p send remote wake-up bit set to force an external interrupt on the usb controller for remote wake up purpose. an upstream resume is send only if the bit rmwupe is set, all usb clocks are enabled and the usb bus was in suspend state for at least 5 ms. see uprsm below. cleared by software. 4- reserved the value read from this bit is always 0. do not set this bit. 3uprsm upstream resume bit (read only) set by hardware when sdrmwup has been set and if rmwupe is enabled. cleared by hardware after the upstream resume has been sent. 2rmwupe remote wake-up enable bit set to enabled request an upstream resume signaling to the host. clear after the upstream resume has been indicated by rsminpr. note: do not set this bit if the host has not set the device_remote_wakeup feature for the device. 1confg configuration bit this bit should be set by the device firmware after a set_configuration request with a non-zero val ue has been correctly processed. it should be cleared by the device firmware when a set_configuration request with a zero value is received. it is cleared by hardware on hardware reset or when an usb reset is detected on the bus (se0 state for at least 32 full speed bit times: typically 2.7 s). 0fadden function address enable bit this bit should be set by the device firmware after a successful status phase of a set_address transaction. it should not be cleared afterwards by the device firmware. it is cleared by hardware on hardware reset or when an usb reset is received (see above). when this bit is cleared, the def ault function address is used (0).
102 at8xc51snd1c 4109h?8051?01/05 table 11. usbaddr register usbaddr (s:c6h) ? usb address register reset value = 0000 0000b table 12. usbint register usbint (s:bdh) ? usb global interrupt register reset value = 0000 0000b 76543210 fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit number bit mnemonic description 7fen function enable bit set to enable the function. the device firmware should set this bit after it has received a usb reset and participate in the following configuration process with the default address (fen is reset to 0). cleared by hardware at power-up, should not be cleared by the device firmware once set. 6 - 0 uadd6:0 usb address bits this field contains the default address (0) after power-up or usb bus reset. it should be written with the value set by a set_address request received by the device firmware. 76543210 - - wupcpu eorint sofint - - spint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not set these bits. 5 wupcpu wake up cpu interrupt flag set by hardware when the usb controlle r is in suspend state and is re- activated by a non-idle signal from usb line (not by an upstream resume). this triggers a usb interrupt when ewupcpu is set in the usbien. cleared by software after re-enabling all usb clocks. 4eorint end of reset interrupt flag set by hardware when a end of reset has been detected by the usb controller. this triggers a usb interrupt when eeorint is set in usbien. cleared by software. 3sofint start of frame interrupt flag set by hardware when an usb start of frame packet (sof) has been properly received. this triggers a usb interr upt when esofint is set in usbien. cleared by software. 2 - 1 - reserved the value read from these bits is always 0. do not set these bits. 0spint suspend interrupt flag set by hardware when a usb suspend (idl e bus for three frame periods: a j state for 3 ms) is detected. this triggers a usb interrupt when espint is set in usbien. cleared by software.
103 at8xc51snd1c 4109h?8051?01/05 table 13. usbien register usbien (s:beh) ? usb global interrupt enable register reset value = 0001 0000b table 14. uepnum register uepnum (s:c7h) ? usb endpoint number reset value = 0000 0000b 76543210 - - ewupcpu eeorint esofint - - espint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not set these bits. 5 ewupcp u wake up cpu interrupt enable bit set to enable the wake up cpu interrupt. clear to disable the wake up cpu interrupt. 4eeofint end of reset interrupt enable bit set to enable the end of reset interrupt. this bit is set after reset. clear to disable end of reset interrupt. 3esofint start of frame interrupt enable bit set to enable the sof interrupt. clear to disable the sof interrupt. 2 - 1 - reserved the value read from these bits is always 0. do not set these bits. 0espint suspend interrupt enable bit set to enable suspend interrupt. clear to disable suspend interrupt. 76543210 ------epnum1epnum0 bit number bit mnemonic description 7 - 2 - reserved the value read from these bits is always 0. do not set these bits. 1 - 0 epnum1: 0 endpoint number bits set this field with the number of the endpoint which should be accessed when reading or writing to registers ueps tax, uepdatx, ubyctx or uepconx.
104 at8xc51snd1c 4109h?8051?01/05 table 15. uepconx register uepconx (s:d4h) ? usb endpoint x control register (x = epnum set in uepnum) reset value = 1000 0000b 76543210 epen nakien nakout nakin dtgl epdir eptype1 eptype0 bit number bit mnemonic description 7epen endpoint enable bit set to enable the endpoint according to the device configuration. endpoint 0 should always be enabled after a hardware or usb bus reset and participate in the device configuration. clear to disable the endpoint acco rding to the device configuration. 6nakien nak interrupt enable set this bit to enable nak in or nak out interrupt. clear this bit to disable nak in or nak out interrupt. 5nakout nak out received this bit is set by hardware when an nak handshake has been sent in response of a out request from the host. this triggers a usb interrupt when nakien is set. this bit should be cleared by software. 4nakin nak in received this bit is set by hardware when an nak handshake has been sent in response of a in request from the host. this tri ggers a usb interrupt when nakien is set. this bit should be cleared by software. 3dtgl data toggle status bit (read-only) set by hardware when a data1 packet is received. cleared by hardware when a data0 packet is received. 2epdir endpoint direction bit set to configure in direction for bulk, interrupt and isochronous endpoints. clear to configure out direction for bulk, interrupt and isochronous endpoints. this bit has no effect for control endpoints. 1-0 eptype1: 0 endpoint type bits set this field according to the endpoint configuration (endpoint 0 should always be configured as control): 00 control endpoint 01 isochronous endpoint 10 bulk endpoint 11 interrupt endpoint
105 at8xc51snd1c 4109h?8051?01/05 table 16. uepstax register uepstax (s:ceh) ? usb endpoint x status and control register (x = epnum set in uepnum ) 76543210 dir rxoutb1 stallrq txrdy stlcrc rxsetup rxoutb0 txcmp bit number bit mnemonic description 7dir control endpoint direction bit this bit is relevant only if the endpoint is configured in control type. set for the data stage. clear otherwise. note: this bit should be configured on rxse tup interrupt before any other bit is changed. this also determines the status phase (in for a control write and out for a control read). this bit should be cl eared for status stage of a control out transaction. 6 rxoutb1 received out data bank 1 for endpoints 1 and 2 (ping-pong mode) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 1 (only in ping-pong mode). then, the endpoint interrupt is triggered if enabled and all the following out packets to the endpoint bank 1 are rejected (nak?ed) until this bit has been cleared, excepted for isochronous endpoints. this bit should be cleared by the devic e firmware after reading the out data from the endpoint fifo.
106 at8xc51snd1c 4109h?8051?01/05 reset value = 0000 0000b 5stallrq stall handshake request bit set to send a stall answer to the hos t for the next handshake. clear otherwise. 4txrdy tx packet ready control bit set after a packet has been written into the endpoint fifo for in data transfers. data should be written into the endpoint fifo only after this bit has been cleared. set this bit without writing data to the endpoint fifo to send a zero length packet, which is generally recommended and may be required to terminate a transfer when the length of the last data packet is equal to maxpacketsize (e.g. for control read transfers). cleared by hardware, as soon as the packet has been sent for isochronous endpoints, or after the host has acknowledged the packet for control, bulk and interrupt endpoints. 3 stlcrc stall sent interrupt flag/crc error interrupt flag for control, bulk and interrupt endpoints: set by hardware after a stall hands hake has been sent as requested by stallrq. then, the endpoint interrupt is triggered if enabled in uepien. cleared by hardware when a setup packet is received (see rxsetup). for isochronous endpoints: set by hardware if the last data receiv ed is corrupted (crc error on data). then, the endpoint interrupt is triggered if enabled in uepien. cleared by hardware when a non corrupted data is received. 2 rxsetup received setup interrupt flag set by hardware when a valid setup packet has been received from the host. then, all the other bits of the regist er are cleared by har dware and the endpoint interrupt is triggered if enabled in uepien. clear by software after reading the setup data from the endpoint fifo. 1 rxoutb0 received out data bank 0 (see also rxoutb1 bit for ping-pong endpoints) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 0. then, the endpoint interrupt is triggered if enabled and all the following out packets to the endpoint bank 0 are rejected (nak?ed) until this bit has been cleared, excepted for isochronous endpoints. however, for control endpoints, an early setup transaction may overwrite the content of the endpoint fifo, even if its data packet is received while this bit is set. this bit should be cleared by the devic e firmware after reading the out data from the endpoint fifo. 0txcmp transmitted in data complete interrupt flag set by hardware after an in packet has been transmitted for isochronous endpoints and after it has been accepted (ack?ed) by the host for control, bulk and interrupt endpoints. then, the endpoint interrupt is triggered if enabled in uepien. clear by software before setting again txrdy. bit number bit mnemonic description
107 at8xc51snd1c 4109h?8051?01/05 table 17. ueprst register ueprst (s:d5h) ? usb endpoint fifo reset register reset value = 0000 0000b table 18. uepien register uepien (s:c2h) ? usb endpoint interrupt enable register reset value = 0000 0000b 76543210 -----ep2rstep1rstep0rst bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set these bits. 2 ep2rst endpoint 2 fifo reset set and clear to reset the endpoint 2 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 1 ep1rst endpoint 1 fifo reset set and clear to reset the endpoint 1 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 0 ep0rst endpoint 0 fifo reset set and clear to reset the endpoint 0 fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. 76543210 -----ep2inteep1inteep0inte bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set these bits. 2ep2inte endpoint 2 interrupt enable bit set to enable the interrupts for endpoint 2. clear this bit to disable the interrupts for endpoint 2. 1ep1inte endpoint 1 interrupt enable bit set to enable the interrupts for the endpoint 1. clear to disable the interrupts for the endpoint 1. 0ep0inte endpoint 0 interrupt enable bit set to enable the interrupts for the endpoint 0. clear to disable the interrupts for the endpoint 0.
108 at8xc51snd1c 4109h?8051?01/05 table 19. uepint register uepint (s:f8h read-only) ? usb endpoint interrupt register reset value = 0000 0000b table 20. uepdatx register uepdatx (s:cfh) ? usb endpoint x fifo data register (x = epnum set in uepnum) reset value = xxh 76543210 -----ep2intep1intep0int bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set these bits. 2ep2int endpoint 2 interrupt flag this bit is set by hardware when an endpo int interrupt source has been detected on the endpoint 2. the endpoint interrupt sources are in the uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep2ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoint interrupt sources are cleared. 1ep1int endpoint 1 interrupt flag this bit is set by hardware when an endpo int interrupt source has been detected on the endpoint 1. the endpoint interrupt sources are in the uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep1ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoint interrupt sources are cleared. 0ep0int endpoint 0 interrupt flag this bit is set by hardware when an endpo int interrupt source has been detected on the endpoint 0. the endpoint interrupt sources are in the uepstax register and can be: txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep0ie bit in the uepien register is set. this bit is cleared by hardware when all the endpoint interrupt sources are cleared. 76543210 fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 bit number bit mnemonic description 7 - 0 fdat7:0 endpoint x fifo data data byte to be written to fifo or data byte to be read from the fifo, for the endpoint x (see epnum).
109 at8xc51snd1c 4109h?8051?01/05 table 21. ubyctx register ubyctx (s:e2h) ? usb endpoint x byte count register (x = epnum set in uepnum) reset value = 0000 0000b table 22. ufnuml register ufnuml (s:bah, read-only) ? usb frame number low register reset value = 00h 76543210 - byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7- reserved the value read from this bits is always 0. do not set this bit. 6 - 0 byct7:0 byte count byte count of a received data packet. this byte count is equal to the number of data bytes received after the data pid. 76543210 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 bit number bit mnemonic description 7 - 0 fnum7:0 frame number lower 8 bits of the 11-bit frame number.
110 at8xc51snd1c 4109h?8051?01/05 table 23. ufnumh register ufnumh (s:bbh, read-only) ? usb frame number high register reset value = 00h table 24. usbclk register usbclk (s:eah) ? usb clock divider register reset value = 0000 0000b 76543210 - - crcok crcerr - fnum10 fnum9 fnum8 bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set these bits. 5 crcok frame number crc ok bit set by hardware after a non corrupted frame number in start of frame packet is received. updated after every start of frame packet reception. note: the start of frame interrupt is generated just after the pid receipt. 4 crcerr frame number crc error bit set by hardware after a corrupted frame nu mber in start of frame packet is received. updated after every start of frame packet reception. note: the start of frame interrupt is generated just after the pid receipt. 3- reserved the value read from this bits is always 0. do not set this bit. 2-0 fnum10:8 frame number upper 3 bits of the 11-bit frame number. it is provided in the last received sof packet. fnum does not change if a corrupted sof is received. 76543210 ------us bcd1 usbcd0 bit number bit mnemonic description 7 - 2 - reserved the value read from these bits is always 0. do not set these bits. 1 - 0 usbcd1:0 usb controller clock divider 2-bit divider for usb controller clock generation.
111 at8xc51snd1c 4109h?8051?01/05 17. multimedia card controller the at8xc51snd1c implements a multimedia card (mmc) controller. the mmc is used to store mp3 encoded audio files in re movable flash memory cards that can be easily plugged or removed from the application. 17.1 card concept the basic multimedia card concept is based on transferring data via a minimum number of signals. 17.1.1 card signals the communication signals are: clk: with each cycle of this signal a one bit transfer on the command and data lines is done. the frequency may vary from zero to the maximum clock frequency. cmd: is a bi-directional command channel used for card initialization and data transfer commands. the cmd signal has 2 operation modes: open-drain for initialization mode and push-pull for fast command transfer. commands are sent from the multimedia card bus master to the card and responses from the cards to the host. dat: is a bi-directional data channel. the dat signal operates in push-pull mode. only one card or the host is driving this signal at a time. 17.1.2 card registers within the card interface five registers are defined: ocr, cid, csd, rca and dsr. these can be accessed only by the corresponding commands. the 32-bit operation conditions register (ocr) stores the v dd voltage profile of the card. the register is optional and can be read only. the 128-bit wide cid register carries the card identification information (card id) used during the card identification procedure. the 128-bit wide card-specific data register (csd) provides information on how to access the card contents. the csd defines the data format, error correction type, maxi- mum data access time, data transfer speed, and whether the dsr register can be used. the 16-bit relative card address register (rca) carries the card address assigned by the host during the card identification. this address is used for the addressed host-card communication after the card identification procedure. the 16-bit driver stage register (dsr) can be optionally used to improve the bus per- formance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). 17.2 bus concept the multimedia card bus is designed to connect either solid-state mass-storage mem- ory or i/o-devices in a card format to multimedia applications. the bus implementation allows the coverage of application fields from low-cost systems to systems with a fast data transfer rate. it is a single master bus with a variable number of slaves. the multi- media card bus master is the bus controller and each slave is either a single mass storage card (with possibly different technologies such as rom, otp, flash etc.) or an i/o-card with its own controlling unit (on card) to perform the data transfer. the multimedia card bus also includes power connections to supply the cards. the bus communication uses a special protocol (multimedia card bus protocol) which is applicable for all devices. therefore, the payload data transfer between the host and the cards can be bi-directional.
112 at8xc51snd1c 4109h?8051?01/05 17.2.1 bus lines the multimedia card bus architecture requires all cards to be connected to the same set of lines. no card has an individual connection to the host or other devices, which reduces the connection costs of the multimedia card system. the bus lines can be divided into three groups: power supply: v ss1 and v ss2 , v dd ? used to supply the cards. data transfer: mcmd, mdat ? used for bi-directional communication. clock: mclk ? used to synchronize data transfer across the bus. 17.2.2 bus protocol after a power-on reset, the host must initialize the cards by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: command: a command is a token which starts an operation. a command is transferred serially from the host to the card on the mcmd line. response: a response is a token which is sent from an addressed card (or all connected cards) to the host as an answer to a previously received command. it is transferred serially on the mcmd line. data: data can be transferred from the card to the host or vice-versa. data is transferred serially on the mdat line. card addressing is implemented using a session address assigned during the initializa- tion phase, by the bus controller to all currently connected cards. individual cards are identified by their cid number. this method requires that every card will have an unique cid number. to ensure uniqueness of cids the cid register contains 24 bits (mid and oid fields) which are defined by the mmca. every card manufacturers is required to apply for an unique mid (and optionally oid) number. multimedia card bus data transfers are composed of these tokens. one data transfer is a bus operation. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token, the others transfer their informati on directly within the command or response structure. in this case no data token is present in an operation. the bits on the mdat and the mcmd lines are transferred synchronous to the host clock. 2 types of data transfer commands are defined: sequential commands: these commands initiate a continuous data stream, they are terminated only when a stop command follows on the mcmd line. this mode reduces the command overhead to an absolute minimum. block-oriented commands: these commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop command follows on the mcmd line similarly to the stream read. figure 73 through figure 77 show the different types of operations, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host. figure 73. sequential read operation data stream command response mcmd mdat data stop operation data transfer operation command response stop command
113 at8xc51snd1c 4109h?8051?01/05 figure 74. (multiple) block read operation as shown in figure 75 and figure 76 the data write operation uses a simple busy signal- ling of the write operation duration on the data line (mdat). figure 75. sequential write operation figure 76. multiple block write operation figure 77. no response and no data operation 17.2.3 command token format as shown in figure 78, commands have a fixed code length of 48 bits. each command token is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a high level on mcmd line for a command token (host to card) and succeeded by a 7 - bit crc so that transmission errors can be detected and the operation may be repeated. command content contains the command index and address information or parameters. figure 78. command token format data block mcmd mdat data stop operation block read operation crc multiple block read operation command response command response data block crc data block crc stop command data stream mcmd mdat data stop operation data transfer operation command response command response stop command busy mcmd mdat data stop operation block write operation multiple block write operation busy data block crc data block crc command response command response stop command status busy status command mcmd mdat no data operation no response operation command response 0 total length = 48 bits content crc 1 1
114 at8xc51snd1c 4109h?8051?01/05 table 3. command token format 17.3.1 response token format there are five types of response tokens (r1 to r5). as shown in figure 79, responses have a code length of 48 bits or 136 bits. a response token is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. the command content is preceded by a transmission bit: a low level on mcmd line for a response token (card to host) and succeeded (r1,r2,r4,r5) or not (r3) by a 7 - bit crc. response content contains mirrored command and status information (r1 response), cid register or csd register (r2 response), ocr register (r3 response), or rca regis- ter (r4 and r5 response). figure 79. response token format table 4. r1 response format (normal response) table 5. r2 response format (cid and csd registers) bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?1? - - - ?1? description start bit transmission bit command index argument crc7 end bit bit position 47 46 45:40 39:8 7:1 0 width (bits) 1163271 value ?0? ?0? - - - ?1? description start bit transmission bit command index card status crc7 end bit bit position 135 134 [133:128] [127:1] 0 width (bits) 1 1 6321 value ?0? ?0? ?111111? - ?1? description start bit transmission bit reserved argument end bit 0 total length = 48 bits content crc 0 1 r1, r4, r5 0 total length = 136 bits content = cid or csd crc 0 1 r2 0 total length = 48 bits content 0 1 r3
115 at8xc51snd1c 4109h?8051?01/05 table 6. r3 response format (ocr register) table 7. r4 response format (fast i/o) table 8. r5 response format 17.8.1 data packet format there are 2 types of data packets: stream and block. as shown in figure 80, stream data packets have an indeterminate length while block packets have a fixed length depending on the block length. each data packet is preceded by a start bit: a low level on mcmd line and succeeded by an end bit: a high level on mcmd line. due to the fact that there is no predefined end in stream packets, crc protection is not included in this case. the crc protection algorithm for block data is a 16-bit ccitt polynomial. figure 80. data token format 17.8.2 clock control the mmc bus clock signal can be used by the host to turn the cards into energy saving mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. the host is allowed to lower the clock frequency or shut it down. there are a few restrictions the host must follow: the bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the cards, and the identification frequency defined by the specification document). it is an obvious requirement that the clock must be running for the card to output data or response tokens. after the last multimedia card bus transaction, the host is bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 1 1 6327 1 value ?0? ?0? ?111111? - ?1111111? ?1? description start bit transmission bit reserved ocr register reserved end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 11 63271 value ?0? ?0? ?100111? - - ?1? description start bit transmission bit command index argument crc7 end bit bit position 47 46 [45:40] [39:8] [7:1] 0 width (bits) 1 1 6327 1 value ?0? ?0? ?101000? - - ?1? description start bit transmission bit command index argument crc7 end bit 0 content 1 sequential data crc block data 0 content 1 block length
116 at8xc51snd1c 4109h?8051?01/05 required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. following is a list of the various bus transactions: a command with no response. 8 clocks after the host command end bit. a command with response. 8 clocks after the card command end bit. a read data transaction. 8 clocks after the end bit of the last data block. a write data transaction. 8 clocks after the crc status token. the host is allowed to shut down the clock of a ?busy? card. the card will complete the programming operation regardless of the host clock. however, the host must provide a clock edge for the card to turn off its busy signal. without a clock edge the card (unless previously disconnected by a deselect command-cmd7) will force the mdat line down, forever. 17.9 description the mmc controller interfaces to the c51 core through the following eight special func- tion registers: mmcon0, mmcon1, mmcon2, the three mmc control registers (see table 16 to table 24); mmsta, the mmc status register (see table 19); mmint, the mmc interrupt register (see table 20); mmmsk, the mmc interrupt mask register (see table 21); mmcmd, the mmc command register (see table 22); mmdat, the mmc data register (see table 23); and mmclk, the mmc clock register (see table 24). as shown in figure 81, the mmc controller is divided in four blocks: the clock generator that handles the mclk (formally the mmc clk) output to the card, the command line controller that handles the mcmd (formally the mmc cmd) line traffic to or from the card, the data line controller that handles the mdat (formally the mmc dat) line traffic to or from the card, and the interrupt controller that handles the mmc controller interrupt sources. these blocks are detailed in the following sections. figure 81. mmc controller block diagram 17.10 clock generator the mmc clock is generated by division of the oscillator clock (f osc ) issued from the clock controller block as detailed in section "oscillator", page 12. the division factor is given by mmcd7:0 bits in mmclk register, a value of 0x00 stops the mmc clock. figure 82 shows the mmc clock generator and its output clock calculation formula. osc clock mcmd mclk 8 internal bus mdat command line clock mmc interrupt request generator controller data line controller interrupt controller
117 at8xc51snd1c 4109h?8051?01/05 figure 82. mmc clock generator and symbol as soon as mmcen bit in mmcon2 is set, the mmc controller receives its system clock. the mmc command and data clock is generated on mclk output and sent to the command line and data line controllers. figure 83 shows the mmc controller configura- tion flow. as exposed in section ?clock control?, page 115, mmcd7:0 bits can be used to dynam- ically increase or reduce the mmc clock. figure 83. configuration flow mmcd7:0 mmclk mmc clock mmcclk oscclk mmcd 1 + ---------------------------- - = osc clock mmcen mmcon2.7 controller clock mmc clock mmc clock symbol mmc controller configuration configure mmc clock mmclk = xxh mmcen = 1 flowc = 0
118 at8xc51snd1c 4109h?8051?01/05 17.11 command line controller as shown in figure 84, the command line cont roller is divided in 2 channels: the com- mand transmitter channel that handles the command transmission to the card through the mcmd line and the command receiver channel that handles the response reception from the card through the mcmd line. these channels are detailed in the following sections. figure 84. command line controller block diagram 17.11.1 command transmitter for sending a command to the card, user must load the command index (1 byte) and argument (4 bytes) in the command transmit fifo using the mmcmd register. before starting transmission by setting and clearing the cmden bit in mmcon1 register, user must first configure: respen bit in mmcon1 register to indicate whether a response is expected or not. rfmt bit in mmcon0 register to indicate the response size expected. crcdis bit in mmcon0 register to indicate whether the crc7 included in the response will be computed or not. in order to avoid crc error, crcdis may be set for response that do not include crc7. figure 85 summarizes the command transmission flow. as soon as command transmission is enabled, the cflck flag in mmsta is set indicat- ing that write to the fifo is locked. this mechanism is implemented to avoid command overrun. the end of the command transmission is signalled to you by the eoci flag in mmint register becoming set. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 126. the end of the command transmission also resets the cflck flag. ctptr mmcon0.4 crptr mmcon0.5 mcm d cmden mmcon1.0 tx command line finished state machine data converter // -> serial 5-byte fifo mmcmd tx pointer rfmt mmcon0.1 crcdis mmcon0.0 respen mmcon1.1 data converter serial -> // rx pointer 17 - byte fifo mmcmd cflck mmsta.0 crc7 generator rx command line finished state machine crc7 and format checker crc7s mmsta.2 respfs mmsta.1 eoci mmint.5 eori mmint.6 command transmitter command receiver write read
119 at8xc51snd1c 4109h?8051?01/05 user may abort command loading by setting and clearing the ctptr bit in mmcon0 register which resets the write pointer to the transmit fifo. figure 85. command transmission flow 17.11.2 command receiver the end of the response reception is signalled to you by the eori flag in mmint regis- ter. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 126. when this flag is set, 2 other flags in mmsta register: respfs and crc7s give a status on the response received. respfs indicates if the response format is cor- rect or not: the size is the one expected (48 bits or 136 bits) and a valid end bit has been received, and crc7s indicates if the crc7 computation is correct or not. these flags are cleared when a command is sent to the card and updated when the response has been received. user may abort response reading by setti ng and clearing the crptr bit in mmcon0 register which resets the read pointer to the receive fifo. according to the mmc specification delay between a command and a response (for- mally n cr parameter) can not exceed 64 mmc clock periods. to avoid any locking of the mmc controller when card does not send its response (e.g. physically removed from the bus), user must launch a time-out period to exit from such situation. in case of time- out user may reset the command controller and its internal state machine by setting and clearing the ccr bit in mmcon2 register. this time-out may be disarmed when receiving the response. command transmission load command in buffer mmcmd = index mmcmd = argument configure response respen = x rfmt = x crcdis = x transmit command cmden = 1 cmden = 0
120 at8xc51snd1c 4109h?8051?01/05 17.12 data line controller the data line controller is based on a 16-by te fifo used both by the data transmitter channel and by the data receiver channel. figure 86. data line controller block diagram 17.12.1 fifo implementation the 16-byte fifo is based on a dual 8-byte fifos managed using 2 pointers and four flags indicating the status full and empty of each fifo. pointers are not accessible to user but can be reset at any time by setting and clearing drptr and dtptr bits in mmcon0 register. resetting the pointers is equivalent to abort the writing or reading of data. f1ei and f2ei flags in mmint register si gnal when set that respectively fifo1 and fifo2 are empty. f1fi and f2fi flags in mmint register signal when set that respec- tively fifo1 and fifo2 are full. these flags may generate an mmc interrupt request as detailed in section ?interrupt?. 17.12.2 data configuration before sending or receiving any data, the data line controller must be configured accord- ing to the type of the data transfer considered. this is achieved using the data format bit: dfmt in mmcon0 register. clearing dfmt bit enables the data stream format while setting dfmt bit enables the data block format. in data block format, user must also configure the single or multi-block mode by clearing or setting the mblock bit in mmcon0 register and the block length using blen3:0 bits in mmcon1 according to table 13. figure 87 summarizes the data modes configuration flows. table 13. block length programming mcbi mmint.1 datfs mmsta.3 crc16s mmsta.4 f2fi mmint.3 f2ei mmint.1 dfmt mmcon0.2 mblock mmcon0.3 datdir mmcon1.3 data converter // -> serial blen3:0 mmcon1.7:4 daten mmcon1.2 data line finished state machine data converter serial -> // dtptr mmcon0.6 drptr mmcon0.7 tx pointer rx pointer 8-byte fifo 1 8-byte fifo 2 16-byte fifo mmdat f1ei mmint.0 crc16 and format checker f1fi mmint.2 eofi mmint.4 cbusy mmsta.5 crc16 generator mda t blen3:0 block length (byte) blen = 0000 to 1011 length = 2 blen : 1 to 2048 > 1011 reserved: do not program blen3:0 > 1011
121 at8xc51snd1c 4109h?8051?01/05 figure 87. data controller configuration flows 17.13.1 data transmitter configuration for transmitting data to the card user must first configure the data controller in transmis- sion mode by setting the datdir bit in mmcon1 register. figure 88 summarizes the data stream transmission flows in both polling and interrupt modes while figure 89 summarizes the data block transmission flows in both polling and interrupt modes, these flows assume that block length is greater than 16 data. data loading data is loaded in the fifo by writing to mmdat register. number of data loaded may vary from 1 to 16 bytes. then if necessary (more than 16 bytes to send) user must wait that one fifo becomes empty (f1ei or f2ei set) before loading 8 new data. data transmission transmission is enabled by setting and clearing daten bit in mmcon1 register. data is transmitted immediately if the response has already been received, or is delayed after the response reception if its status is correct. in both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition. according to the mmc specification, the data transfer from the host to the card may not start sooner than 2 mmc clock periods after the card response was received (formally n wr parameter). to address all card types, this delay can be programmed using datd1:0 bits in mmcon2 register from 3 mmc clock periods when datd1:0 bits are cleared to 9 mmc clock periods when datd1:0 bits are set, by step of 2 mmc clock periods. end of transmission the end of a data frame (block or stream) transmission is signalled to you by the eofi flag in mmint register. this flag may generate an mmc interrupt request as detailed in section "interrupt", page 126. in data stream mode, eofi flag is set, after reception of the end bit. this assumes user has previously sent the stop command to the card, which is the only way to stop stream transfer. in data block mode, eofi flag is set, after reception of the crc status token (see figure 79). 2 other flags in mmsta register: datfs and crc16s report a status on the frame sent. datfs indicates if the crc st atus token format is correct or not, and crc16s indicates if the card has found the crc16 of the block correct or not. busy status as shown in figure 79 the card uses a busy token during a block write operation. this busy status is reported to you by the cbusy flag in mmsta register and by the mcbi flag in mmint which is set every time cbusy toggles, i.e. when the card enters and exits its busy state. this flag may generate an mmc interrupt request as detailed in sec- tion "interrupt", page 126. data single block configuration data stream configuration configure format dfmt = 0 data multi-block configuration configure format dfmt = 1 mblock = 1 blen3:0 = xxxxb configure format dfmt = 1 mblock = 0 blen3:0 = xxxxb
122 at8xc51snd1c 4109h?8051?01/05 figure 88. data stream transmission flows send stop command data stream transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data stream initialization fifos filling write 16 data to mmdat data stream transmission isr fifo filling write 8 data to mmdat send stop command no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? start transmission daten = 1 daten = 0 unmask fifos empty f1em = 0 f2em = 0 mask fifos empty f1em = 1 f2em = 1
123 at8xc51snd1c 4109h?8051?01/05 figure 89. data block transmission flows 17.13.2 data receiver configuration to receive data from the card you must first configure the data controller in reception mode by clearing the datdir bit in mmcon1 register. figure 90 summarizes the data stream reception flows in both polling and interrupt modes while figure 91 summarizes the data block reception flows in both polling and interrupt modes, these flows assume that block length is greater than 16 bytes. data reception the end of a data frame (block or stream) reception is signalled to you by the eofi flag in mmint register. this flag may generate an mmc interrupt request as detailed in sec- tion "interrupt", page 126. when this flag is set, 2 other flags in mmsta register: datfs and crc16s give a status on the frame received. datfs indicates if the frame format is correct or not: a valid end bit has been received, and crc16s indicates if the crc16 computation is correct or not. in case of data stream crc16s has no meaning and stays cleared. according to the mmc specification data transmission from the card starts after the access time delay (formally n ac parameter) beginning from the end bit of the read com- mand. to avoid any locking of the mmc controller when card does not send its data (e.g. physically removed from the bus), you must launch a time-out period to exit from such situation. in case of time-out you may reset the data controller and its internal state machine by setting and clearing the dcr bit in mmcon2 register. data block transmission start transmission daten = 1 daten = 0 fifo empty? f1ei or f2ei = 1? fifo filling write 8 data to mmdat no more data to send? fifos filling write 16 data to mmdat a. polling mode data block initialization start transmission daten = 1 daten = 0 fifos filling write 16 data to mmdat data block transmission isr fifo filling write 8 data to mmdat no more data to send? b. interrupt mode fifo empty? f1ei or f2ei = 1? mask fifos empty f1em = 1 f2em = 1 unmask fifos empty f1em = 0 f2em = 0
124 at8xc51snd1c 4109h?8051?01/05 this time-out may be disarmed after receiving 8 data (f1fi flag set) or after receiving end of frame (eofi flag set) in case of block length less than 8 data (1, 2 or 4). data reading data is read from the fifo by reading to mmdat register. each time one fifo becomes full (f1fi or f2fi set), user is requested to flush this fifo by reading 8 data. figure 90. data stream reception flows data stream reception fifo full? f1fi or f2fi = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data stream initialization data stream reception isr fifo reading read 8 data from mmdat send stop command no more data to receive? b. interrupt mode fifo full? f1fi or f2fi = 1? unmask fifos full f1fm = 0 f2fm = 0 send stop command mask fifos full f1fm = 1 f2fm = 1
125 at8xc51snd1c 4109h?8051?01/05 figure 91. data block reception flows 17.13.3 flow control to allow transfer at high speed without taki ng care of cpu oscillator frequency, the flowc bit in mmcon2 allows control of the data flow in both transmission and reception. during transmission, setting the flowc bit has the following effects: mmclk is stopped when both fifos become empty: f1ei and f2ei set. mmclk is restarted when one of the fifos becomes full: f1ei or f2ei cleared. during reception, setting the flowc bit has the following effects: mmclk is stopped when both fifos become full: f1fi and f2fi set. mmclk is restarted when one of the fifos becomes empty: f1fi or f2fi cleared. as soon as the clock is stopped, the mmc bus is frozen and remains in its state until the clock is restored by writing or reading data in mmdat. data block reception start transmission daten = 1 daten = 0 fifo full? f1ei or f2ei = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data block initialization start transmission daten = 1 daten = 0 data block reception isr fifo reading read 8 data from mmdat no more data to receive? b. interrupt mode fifo full? f1ei or f2ei = 1? mask fifos full f1fm = 1 f2fm = 1 unmask fifos full f1fm = 0 f2fm = 0
126 at8xc51snd1c 4109h?8051?01/05 17.14 interrupt 17.14.1 description as shown in figure 92, the mmc controller implements eight interrupt sources reported in mcbi, eori, eoci, eofi, f2fi, f1fi, and f2ei flags in mmcint register. these flags are detailed in the previous sections. all these sources are maskable separately using mcbm, eorm, eocm, eofm, f2fm, f1fm, and f2em mask bits respectively in mmmsk register. the interrupt request is generated each time an unmasked flag is set, and the global mmc controller interrupt enable bit is set (emmc in ien1 register). reading the mmint register automatically clears the interrupt flags (acknowledgment). this implies that register content must be saved and tested interrupt flag by interrupt flag to be sure not to forget any interrupts. figure 92. mmc controller interrupt system mmc interface interrupt reques t mcbi mmint.7 eocm mmmsk.5 emmc ien1.0 mcbm mmmsk.7 eorm mmmsk.6 eofi mmint.4 f2fm mmmsk.3 eofm mmmsk.4 eori mmint.6 f2fi mmint.3 eoci mmint.5 f2em mmmsk.1 f1fm mmmsk.2 f1ei mmint.0 f1em mmmsk.0 f1fi mmint.2 f2ei mmint.1
127 at8xc51snd1c 4109h?8051?01/05 17.15 registers table 16. mmcon0 register mmcon0 (s:e4h) ? mmc control register 0 reset value = 0000 0000b 76543210 drptr dtptr crptr ctptr mblock dfmt rfmt crcdis bit number bit mnemonic description 7 drptr data receive pointer reset bit set to reset the read pointer of the data fifo. clear to release the read pointer of the data fifo. 6 dtptr data transmit pointer reset bit set to reset the write pointer of the data fifo. clear to release the write pointer of the data fifo. 5 crptr command receive pointer reset bit set to reset the read pointer of the receive command fifo. clear to release the read pointer of the receive command fifo. 4 ctptr command transmit pointer reset bit set to reset the write pointer of the transmit command fifo. clear to release the read pointer of the transmit command fifo. 3mblock multi-block enable bit set to select multi-block data format. clear to select single block data format. 2dfmt data format bit set to select the block-oriented data format. clear to select the stream data format. 1rfmt response format bit set to select the 48-bit response format. clear to select the 136-bit response format. 0 crcdis crc7 disable bit set to disable the crc7 computation when receiving a response. clear to enable the crc7 computation when receiving a response.
128 at8xc51snd1c 4109h?8051?01/05 table 17. mmcon1 register mmcon1 (s:e5h) ? mmc control register 1 reset value = 0000 0000b table 18. mmcon2 register mmcon2 (s:e6h) ? mmc control register 2 reset value = 0000 0000b 76543210 blen3 blen2 blen1 blen0 datdir daten respen cmden bit number bit mnemonic description 7 - 4 blen3:0 block length bits refer to table 13 for bits description. do not program value > 1011b 3datdir data direction bit set to select data transfer from host to card (write mode). clear to select data transfer from card to host (read mode). 2daten data transmission enable bit set and clear to enable data transmission immediately or after response has been received. 1 respen response enable bit set and clear to enable the reception of a response following a command transmission. 0cmden command transmission enable bit set and clear to enable transmission of the command fifo to the card. 76543210 mmcen dcr ccr - - datd1 datd0 flowc bit number bit mnemonic description 7mmcen mmc clock enable bit set to enable the mclk clocks and activate the mmc controller. clear to disable the mmc clocks and freeze the mmc controller. 6 dcr data controller reset bit set and clear to reset the data line controller in case of transfer abort. 5 ccr command controller reset bit set and clear to reset the command line controller in case of transfer abort. 4-3 - reserved the value read from these bits is always 0. do not set these bits. 2-1 datd1:0 data transmission delay bits used to delay the data transmission after a response from 3 mmc clock periods (all bits cleared) to 9 mmc clock periods (all bits set) by step of 2 mmc clock periods. 0flowc mmc flow control bit set to enable the flow control during data transfers. clear to disable the flow control during data transfers.
129 at8xc51snd1c 4109h?8051?01/05 table 19. mmsta register mmsta (s:deh read only) ? mmc control and status register reset value = 0000 0000b 76543210 - - cbusy crc16s datfs crc7s respfs cflck bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not set these bits. 5cbusy card busy flag set by hardware when the card sends a busy state on the data line. cleared by hardware when the card no more sends a busy state on the data line. 4 crc16s crc16 status bit transmission mode set by hardware when the tok en response reports a good crc. cleared by hardware when the to ken response reports a bad crc. reception mode set by hardware when the crc16 received in the data block is correct. cleared by hardware when the crc16 receiv ed in the data block is not correct. 3datfs data format status bit transmission mode set by hardware when the format of the token response is correct. cleared by hardware when the format of the token response is not correct. reception mode set by hardware when the format of the frame is correct. cleared by hardware when the format of the frame is not correct. 2 crc7s crc7 status bit set by hardware when the crc7 com puted in the response is correct. cleared by hardware when the crc7 comput ed in the response is not correct. this bit is not relevant when crcdis is set. 1 respfs response format status bit set by hardware when the format of a response is correct. cleared by hardware when the format of a response is not correct. 0cflck command fifo lock bit set by hardware to signal user not to write in the transmit command fifo: busy state. cleared by hardware to signal user the transmit command fifo is available: idle state.
130 at8xc51snd1c 4109h?8051?01/05 table 20. mmint register mmint (s:e7h read only) ? mmc interrupt register reset value = 0000 0011b 76543210 mcbi eori eoci eofi f2fi f1fi f2ei f1ei bit number bit mnemonic description 7mcbi mmc card busy interrupt flag set by hardware when the card enters or exits its busy state (when the busy signal is asserted or deasserted on the data line). cleared when reading mmint. 6eori end of response interrupt flag set by hardware at the end of response reception. cleared when reading mmint. 5eoci end of command interrupt flag set by hardware at the end of command transmission. clear when reading mmint. 4eofi end of frame interrupt flag set by hardware at the end of fr ame (stream or block) transfer. clear when reading mmint. 3f2fi fifo 2 full interrupt flag set by hardware when second fifo becomes full. cleared by hardware when second fifo becomes empty. 2f1fi fifo 1 full interrupt flag set by hardware when fi rst fifo becomes full. cleared by hardware when fi rst fifo becomes empty. 1f2ei fifo 2 empty interrupt flag set by hardware when second fifo becomes empty. cleared by hardware when second fifo becomes full. 0f1ei fifo 1 empty interrupt flag set by hardware when firs t fifo becomes empty. cleared by hardware when first fifo becomes full.
131 at8xc51snd1c 4109h?8051?01/05 table 21. mmmsk register mmmsk (s:dfh) ? mmc interrupt mask register reset value = 1111 1111b table 22. mmcmd register mmcmd (s:ddh) ? mmc command register reset value = 1111 1111b 76543210 mcbm eorm eocm eofm f2fm f1fm f2em f1em bit number bit mnemonic description 7mcbm mmc card busy interrupt mask bit set to prevent mcbi flag from generating an mmc interrupt. clear to allow mcbi flag to generate an mmc interrupt. 6eorm end of response interrupt mask bit set to prevent eori flag from generating an mmc interrupt. clear to allow eori flag to generate an mmc interrupt. 5eocm end of command interrupt mask bit set to prevent eoci flag from generating an mmc interrupt. clear to allow eoci flag to generate an mmc interrupt. 4eofm end of frame interrupt mask bit set to prevent eofi flag from generating an mmc interrupt. clear to allow eofi flag to generate an mmc interrupt. 3f2fm fifo 2 full interrupt mask bit set to prevent f2fi flag from generating an mmc interrupt. clear to allow f2fi flag to generate an mmc interrupt. 2f1fm fifo 1 full interrupt mask bit set to prevent f1fi flag from generating an mmc interrupt. clear to allow f1fi flag to generate an mmc interrupt. 1f2em fifo 2 empty interrupt mask bit set to prevent f2ei flag from generating an mmc interrupt. clear to allow f2ei flag to generate an mmc interrupt. 0f1em fifo 1 empty interrupt mask bit set to prevent f1ei flag from generating an mmc interrupt. clear to allow f1ei flag to generate an mmc interrupt. 76543210 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 bit number bit mnemonic description 7 - 0 mc7:0 mmc command receive byte output (read) register of the response fifo. mmc command transmit byte input (write) register of the command fifo.
132 at8xc51snd1c 4109h?8051?01/05 table 23. mmdat register mmdat (s:dch) ? mmc data register reset value = 1111 1111b table 24. mmclk register mmclk (s:edh) ? mmc clock divider register reset value = 0000 0000b 76543210 md7 md6 md5 md4 md3 md2 md1 md0 bit number bit mnemonic description 7 - 0 md7:0 mmc data byte input (write) or output (read) register of the data fifo. 76543210 mmcd7 mmcd6 mmcd5 mmcd4 mmcd3 mmcd2 mmcd1 mmcd0 bit number bit mnemonic description 7 - 0 mmcd7:0 mmc clock divider 8-bit divider for mmc clock generation.
133 at8xc51snd1c 4109h?8051?01/05 18. ide/atapi interface the at8xc51snd1c provides an ide/atapi interface allowing connection of devices such as cd-rom reader, compactflash cards, hard disk drive, etc. it consists of a 16- bit data transfer (read or write) between the at8xc51snd1c and the ide device. 18.1 description the ide interface mode is enabled by setting the ext16 bit in auxr (see figure 9, page 31). as soon as this bit is set, all movx instructions read or write are done in a 16- bit mode compare to the standard 8-bit mode. p0 carries the low order multiplexed address and data bus (a7:0, d7:0) while p2 carries the high order multiplexed address and data bus (a15:8, d15:8). when writing data in ide mode, the acc contains d7:0 data (as in 8-bit mode) while dat16h register (see table 4) contains d15:8 data. when reading data in ide mode, d7:0 data is returned in acc while d15:8 data is returned in dat16h. figure 93 shows the ide read bus cycle while figure 94 shows the ide write bus cycle. for simplicity, these figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. for ide bus cycle timing parameters refer to the section ?ac characteristics?. ide cycle takes 6 cpu clock periods which is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in x2 mode. for further information on x2 mode, refer to the section ?x2 feature?, page 12. slow ide devices can be accessed by stretching the read and write cycles. this is done using the m0 bit in auxr. setting this bit changes the width of the rd and wr signals from 3 to 15 cpu clock periods. figure 93. ide read waveforms notes: 1. rd signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page access mode), p2 outputs sfr content instead of dph. ale p0 p2 rd (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3) d15:8 p2
134 at8xc51snd1c 4109h?8051?01/05 figure 94. ide write waveforms notes: 1. wr signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. 3. when executing movx @dptr instruction, if dphdis is set (page access mode), p2 outputs sfr content instead of dph. 18.1.1 ide device connection figure 95 and figure 96 show 2 examples on how to interface up to 2 ide devices to the at8xc51snd1c. in both examples p0 carries ide low order data bits d7:0, p2 carries ide high order data bits d15:8, while rd and wr signals are respectively connected to the ide nior and niow signals. other ide control signals are generated by the exter- nal address latch outputs in the first example while they are generated by some port i/os in the second one. using an external latch will achieve higher transfer rate. figure 95. ide device connection example 1 figure 96. ide device connection example 2 ale p0 p2 wr (1) dpl or ri d7:0 p2 cpu clock dph or p2 (2),(3) d15:8 p2 p2 p0 d15-8 a2:0 ale niow nior rd wr d7:0 ncs1:0 nreset d15-8 a2:0 niow nior d7:0 ncs1:0 nreset latch ide device 0 ide device 1 at8xc51snd1c px.y p2/a15:8 p0/ad7:0 d15-8 a2:0 p4.5 niow nior rd wr d7:0 ncs1:0 nreset d15-8 a2:0 niow nior d7:0 ncs1:0 nreset p4.2:0 p4.4:3 ide device 0 at8xc51snd1c ide device 1
135 at8xc51snd1c 4109h?8051?01/05 table 2. external data memory interface signals 18.3 registers table 4. dat16h register dat16h (s:f9h) ? data 16 high order byte reset value =xxxx xxxxb signal name type description alternate function a15:8 i/o address lines upper address lines fo r the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the ide interface. p0.7:0 ale o address latch enable ale signals indicates that valid address information is available on lines ad7:0. - rd o read read signal output to external data memory. p3.7 wr o write write signal output to external memory. p3.6 76543210 d15 d14 d13 d12 d11 d10 d9 d8 bit number bit mnemonic description 7 - 0 d15:8 data 16 high order byte when ext16 bit is set, dat16h is set by software with the high order data byte prior any movx write instruction. when ext16 bit is set, dat16h contains the high order data byte after any movx read instruction.
136 at8xc51snd1c 4109h?8051?01/05 19. serial i/o port the serial i/o port in the at8xc51snd1c provides both synchronous and asynchro- nous communication modes. it operates as a synchronous receiver and transmitter in one single mode (mode 0) and operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous modes support framing error detection and multiprocessor communication with auto- matic address recognition. 19.1 mode selection sm0 and sm1 bits in scon register (see figure 11) are used to select a mode among the single synchronous and the three asynchronous modes according to table 2. table 2. serial i/o port mode selection 19.3 baud rate generator depending on the mode and the source selection, the baud rate can be generated from either the timer 1 or the internal baud rate generator. the timer 1 can be used in modes 1 and 3 while the internal baud rate generator can be used in modes 0, 1 and 3. the addition of the internal baud rate generator allows freeing of the timer 1 for other purposes in the application. it is highly recommended to use the internal baud rate generator as it allows higher and more accurate baud rates than timer 1. baud rate formulas depend on the modes selected and are given in the following mode sections. 19.3.1 timer 1 when using timer 1, the baud rate is derived from the overflow of the timer. as shown in figure 97 timer 1 is used in its 8-bit auto-reload mode (detailed in section "mode 2 (8-bit timer with auto-reload)", page 55). smod1 bit in pcon register allows doubling of the generated baud rate. figure 97. timer 1 baud rate generator block diagram sm0 sm1 mode description baud rate 0 0 0 synchronous shift register fixed/variable 0 1 1 8-bit uart variable 1 0 2 9-bit uart fixed 1 1 3 9-bit uart variable tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int1 t1 per clock 6 0 1 smod1 pcon.7 2 t1 clock to seri al port
137 at8xc51snd1c 4109h?8051?01/05 19.3.2 internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the over- flow of the timer. as shown in figure 98 the internal baud rate generator is an 8-bit auto-reload timer fed by the peripheral cloc k or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register (see table 15). the internal baud rate generator is enabled by setting bbr bit in bdrcon register. smod1 bit in pcon reg- ister allows doubling of the generated baud rate. figure 98. internal baud rate generator block diagram 19.4 synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the i/0 capabilities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received least-significant bit (lsb) first. shifts occur at a fixed baud rate (see section "baud rate selection (mode 0)", page 138). figure 99 shows the serial port block diagram in mode 0. figure 99. serial i/o port block diagram (mode 0) 19.4.1 transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 100, writing the byte to transmit to sbuf register starts the trans- mission. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the eighth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) per clock 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 2 to seri al port brg clock tx d rx d sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 per clock baud rate controller
138 at8xc51snd1c 4109h?8051?01/05 figure 100. transmission waveforms (mode 0) 19.4.2 reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and setting the ren bit. as shown in figure 101, clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after eight samplings, the msb (d7) is shifted into the shift register, and hardware asserts ri bit to indicate a completed recep- tion. software can then read the received byte from sbuf register. figure 101. reception waveforms (mode 0) 19.4.3 baud rate selection (mode 0) in mode 0, the baud rate can be either, fixed or variable. as shown in figure 102, the selection is done using m0src bit in bdrcon register. figure 103 gives the baud rate calculation formulas for each baud rate source. figure 102. baud rate source selection (mode 0) figure 103. baud rate formulas (mode 0) write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7 write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri 0 1 m0src bdrcon.0 per clock 6 to serial port ibrg clock baud_rate= 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl= 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per a. fixed formula b. variable formula baud_rate = 6 f per
139 at8xc51snd1c 4109h?8051?01/05 19.5 asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and 2 9-bit asynchronous modes of operation. figure 104 shows the serial port block diagram in such asynchronous modes. figure 104. serial i/o port block diagram (modes 1, 2 and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame (see figure 105) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a data is received, the stop bit is read in the rb8 bit in scon register. figure 105. data frame format (mode 1) modes 2 and 3 modes 2 and 3 are full-duplex, asynchronous modes. the data frame (see figure 106) consists of 11 bits: one start bit, eight data bits (transmitted and received lsb first), one programmable ninth data bit and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is wr itten to tb8 bit in scon register. alterna- tively, you can use the ninth bit can be used as a command/data flag. figure 106. data frame format (modes 2 and 3) 19.5.1 transmission (modes 1, 2 and 3) to initiate a transmission, write to scon register, set the sm0 and sm1 bits according to table 2, and set the ninth bit by writing to tb8 bit. then, writing the byte to be trans- mitted to sbuf register starts the transmission. 19.5.2 reception (modes 1, 2 and 3) to prepare for reception, write to scon register, set the sm0 and sm1 bits according to table 2, and set the ren bit. the actual reception is then initiated by a detected high-to- low transition on the rxd pin. tb8 scon.3 ibrg clock rx d tx d sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock per clock m ode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7
140 at8xc51snd1c 4109h?8051?01/05 19.5.3 framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register as shown in figure 107. when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by 2 devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only software or a chip reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing error detection feature is enabled, ri rises on stop bit instead of the last data bit as detailed in figure 113. figure 107. framing error block diagram 19.5.4 baud rate selection (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 108 the selection is done using rbck and tbck bits in bdrcon register. figure 109 gives the baud rate calculation formulas for each baud rate source while table 6 details internal baud rate generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. figure 108. baud rate source selection (modes 1 and 3) figure 109. baud rate formulas (modes 1 and 3) sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock rx port 0 1 tbck bdrcon.3 t1 clock to seri al ibrg clock tx port 16 16 baud_rate= 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl= 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per baud_rate= 6 ? 32 ? (256 -th1) 2 smod1 ? f per th1= 256 - 192 ? baud_rate 2 smod1 ? f per a. ibrg formula b. t1 formula
141 at8xc51snd1c 4109h?8051?01/05 notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . 19.6.1 baud rate selection (mode 2) in mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the peripheral clock frequency. as shown in figure 110 the selection is done using smod1 bit in pcon register. figure 111 gives the baud rate calculation formula depending on the selection. figure 110. baud rate generator selection (mode 2) table 6. internal baud rate generator value baud rate f per = 6 mhz (1) f per = 8 mhz (1) f per = 10 mhz (1) spd smod1 brl error % spd smod1 brl error % spd smod1 brl error % 115200 - ----------- 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 baud rate f per = 12 mhz (2) f per = 16 mhz (2) f per = 20 mhz (2) spd smod1 brl error % spd smod1 brl error % spd smod1 brl error % 115200 - - - - 1 1 247 3.55 1 1 245 1.36 57600 1 1 243 0.16 1 1 239 2.12 1 1 234 1.36 38400 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 19200 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 0 126 0.16 0 1 smod1 pcon.7 per clock 2 16 to serial port
142 at8xc51snd1c 4109h?8051?01/05 figure 111. baud rate formula (mode 2) 19.7 multiprocessor communication (modes 2 and 3) modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. to enable this feature, set sm2 bit in scon register. when the multiprocessor communica- tion feature is enabled, the serial port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). this allows the at8xc51snd1c to function as a slave processor in an environment where multiple slave processors share a single serial line. when the multiprocessor communication feature is enabled, the receiver ignores frames with the ninth bit clear. the receiver exam ines frames with the ninth bit set for an address match. if the received address matches the slaves address, the receiver hard- ware sets rb8 and ri bits in scon register, generating an interrupt. the addressed slave?s software then clears sm2 bit in scon register and prepares to receive the data bytes. the other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses. 19.8 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, the automatic address recognition feature in mode 1 may be enabled. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e, setting sm2 bit in scon register in mode 0 has no effect). 19.8.1 given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given address. the don?t care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr = 0101 0110b saden = 1111 1100b given = 0101 01xxb baud_rate= 32 2 smod1 ? f per
143 at8xc51snd1c 4109h?8051?01/05 the following is an example of how to use given addresses to address different slaves: slave a:saddr = 1111 0001b saden = 1111 1010b given = 1111 0x0xb slave b:saddr = 1111 0011b saden = 1111 1001b given = 1111 0xx1b slave c:saddr = 1111 0011b saden = 1111 1101b given = 1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to com- municate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 19.8.2 broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr = 0101 0110b saden = 1111 1100b (saddr | saden)=1111 111xb the use of don?t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr = 1111 0001b saden = 1111 1010b given = 1111 1x11b, slave b:saddr = 1111 0011b saden = 1111 1001b given = 1111 1x11b, slave c:saddr = 1111 0010b saden = 1111 1101b given = 1111 1111b, for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send the address ffh. to communicate with slaves a and b, but not slave c, the master must send the address fbh. 19.8.3 reset address on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t care bits). this ensures that the serial
144 at8xc51snd1c 4109h?8051?01/05 port is backwards compatible with the 80c51 microcontrollers that do not support auto- matic address recognition.
145 at8xc51snd1c 4109h?8051?01/05 19.9 interrupt the serial i/o port handles 2 interrupt sources that are the ?end of reception? (ri in scon) and ?end of transmission? (ti in scon) flags. as shown in figure 112 these flags are combined together to appear as a single interrupt source for the c51 core. flags must be cleared by software when executing the serial interrupt service routine. the serial interrupt is enabled by setting es bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. depending on the selected mode and weather the framing error detection is enabled or disabled, ri flag is set during the stop bit or during the ninth bit as detailed in figure 113. figure 112. serial i/o interrupt system figure 113. interrupt waveforms es ien0.4 serial i/o interrupt request ti scon.1 ri scon.0 rxd d0d1d2d3d4d5d6d7 start bit 8-bit data stop bit ri smod0 = x fe smod0 = 1 a. mode 1 b. mode 2 and 3 rxd d0d1d2d3d4d5d6 d8 start bit 9-bit data stop bit ri smod0 = 1 fe smod0 = 1 d7 ri smod0 = 0
146 at8xc51snd1c 4109h?8051?01/05 19.10 registers table 11. scon register scon (s:98h) ? serial control register reset value = 0000 0000b 76543210 fe/sm0 ovr/sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit to select this function, set smod0 bit in pcon register. set by hardware to indicate an invalid stop bit. must be cleared by software. sm0 serial port mode bit 0 refer to table 2 for mode selection. 6sm1 serial port mode bit 1 refer to table 2 for mode selection. 5sm2 serial port mode bit 2 set to enable the multiprocessor communication and automatic address recognition features. clear to disable the multiprocessor communication and automatic address recognition features. 4ren receiver enable bit set to enable reception. clear to disable reception. 3tb8 transmit bit 8 modes 0 and 1: not used. modes 2 and 3: software writes the ninth data bit to be transmitted to tb8. 2rb8 receiver bit 8 mode 0: not used. mode 1 (sm2 cleared): set or cleared by hardware to reflect the stop bit received. modes 2 and 3 (sm2 set): set or cleared by hardware to reflect the ninth bit received. 1ti transmit interrupt flag set by the transmitter after the last data bit is transmitted. must be cleared by software. 0ri receive interrupt flag set by the receiver after the stop bit of a frame has been received. must be cleared by software.
147 at8xc51snd1c 4109h?8051?01/05 table 12. sbuf register sbuf (s:99h) ? serial buffer register reset value = xxxx xxxxb table 13. saddr register saddr (s:a9h) ? slave individual address register reset value = 0000 0000b table 14. saden register saden (s:b9h) ? slave individual address mask byte register reset value = 0000 0000b 76543210 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 bit number bit mnemonic description 7 - 0 sd7:0 serial data byte read the last data received by the serial i/o port. write the data to be transmitted by the serial i/o port. 76543210 sad7 sad6 sad5 sad4 sad3 sad2 sad1 sad0 bit number bit mnemonic description 7 - 0 sad7:0 slave individual address 76543210 sae7 sae6 sae5 sae4 sae3 sae2 sae1 sae0 bit number bit mnemonic description 7 - 0 sae7:0 slave address mask byte
148 at8xc51snd1c 4109h?8051?01/05 table 15. bdrcon register bdrcon (s:92h) ? baud rate generator control register reset value = xxx0 0000b table 16. brl register brl (s:91h) ? baud rate generator reload register reset value = 0000 0000b 76543210 - - - brr tbck rbck spd m0src bit number bit mnemonic description 7 - 5 - reserved the value read from these bits are indeterminate. do not set these bits. 4brr baud rate run bit set to enable the baud rate generator. clear to disable the baud rate generator. 3tbck transmission baud rate selection bit set to select the baud rate generator as transmission baud rate generator. clear to select the timer 1 as transmission baud rate generator. 2rbck reception baud rate selection bit set to select the baud rate generator as reception baud rate generator. clear to select the timer 1 as reception baud rate generator. 1 spd baud rate speed bit set to select high speed baud rate generation. clear to select low speed baud rate generation. 0m0src mode 0 baud rate source bit set to select the variable baud rate generator in mode 0. clear to select fixed baud rate in mode 0. 76543210 brl7 brl6 brl5 brl4 brl3 brl2 brl1 brl0 bit number bit mnemonic description 7 - 0 brl7:0 baud rate reload value
149 at8xc51snd1c 4109h?8051?01/05 20. synchronous peripheral interface the at8xc51snd1c implements a synchronous peripheral interface with master and slave modes capability. figure 114 shows an spi bus configuration using the at8xc51snd1c as master con- nected to slave peripherals while figure 115 shows an spi bus configuration using the at8xc51snd1c as slave of an other master. the bus is made of three wires connecting all the devices together: master output slave input (mosi): it is used to transfer data in series from the master to a slave. it is driven by the master. master input slave output (miso): it is used to transfer data in series from a slave to the master. it is driven by the selected slave. serial clock (sck): it is used to synchronize the data transmission both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. each slave peripheral is selected by one slave select pin (ss ). if there is only one slave, it may be continuously selected with ss tied to a low level. otherwise, the at8xc51snd1c may select each device by software through port pins (pn.x). special care should be taken not to select 2 slaves at the same time to avoid bus conflicts. figure 114. typical master spi bus configuration figure 115. typical slave spi bus configuration at8xc51snd1c dataflash 1 ss miso mosi sck p4.0 p4.1 p4.2 pn.z pn.y pn.x so si sck dataflash 2 ss so si sck lcd controller ss so si sck master slave 1 ss miso mosi sck ssn ss1 ss0 so si sck slave 2 ss so si sck at8xc51snd1c slave n ss miso mosi sck
150 at8xc51snd1c 4109h?8051?01/05 20.1 description the spi controller interfaces with the c51 core through three special function registers: spcon, the spi control register (see table 6 ); spsta, the spi status register (see table 7); and spdat, the spi data register (see table 8). 20.1.1 master mode the spi operates in master mode when the mstr bit in spcon is set. figure 116 shows the spi block diagram in master mode. only a master spi module can initiate transmissions. software begins the transmission by writing to spdat. writ- ing to spdat writes to the shift register while reading spdat reads an intermediate register updated at the end of each transfer. the byte begins shifting out on the mosi pin under the control of the bit rate generator. this generator also controls the shift register of the slave peripheral through the sck output pin. as the byte shifts out, another byte shifts in from the slave peripheral on the miso pin. the byte is transmitted most significant bit (msb) first. the end of transfer is signaled by spif being set. when the at8xc51snd1c is the only master on the bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. figure 116. spi master mode block diagram note: mstr bit in spcon is set to select master mode. bit rate generator spr2:0 spcon mosi/p4.1 miso/p4.0 sck/p4.2 cpol spcon.3 spen spcon.6 cpha spcon.2 per clock 8-bit shift register spdat wr iq internal bus spdat rd control and clock logic modf spsta.4 ss /p4.3 ssdis spcon.5 wcol spsta.6 spif spsta.7
151 at8xc51snd1c 4109h?8051?01/05 20.1.2 slave mode the spi operates in slave mode when the mstr bit in spcon is cleared and data has been loaded in spdat. figure 117 shows the spi block diagram in slave mode. in slave mode, before a data transmission occurs, the ss pin of the slave spi must be asserted to low level. ss must remain low until the transmission of the byte is complete. in the slave spi module, data enters the shift register through the mosi pin under the control of the serial clock pro- vided by the master spi module on the sck input pin. when the master starts a transmission, the data in the shift register begins shifting out on the miso pin. the end of transfer is signaled by spif being set. when the at8xc51snd1c is the only slave on the bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. this bit has no effect when cpha is cleared (see section "ss management", page 153). figure 117. spi slave mode block diagram note: 1. mstr bit in spcon is cleared to select slave mode. 20.1.3 bit rate the bit rate can be selected from seven predefined bit rates using the spr2, spr1 and spr0 control bits in spcon according to table 2. these bit rates are derived from the peripheral clock (f per ) issued from the clock controller block as detailed in section "oscillator", page 12. miso/p4.2 mosi/p4.1 ss /p4.3 spif spsta.7 cpol spcon.3 cpha spcon.2 8-bit shift register spdat wr iq internal bus spdat rd sck/p4.2 ssdis spcon.5 control and clock logic
152 at8xc51snd1c 4109h?8051?01/05 table 2. serial bit rates notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . 20.2.1 data transfer the clock polarity bit (cpol in spcon) defines the default sck line level in idle state (1) while the clock phase bit (cpha in spcon) defines the edges on which the input data are sampled and the edges on which the output data are shifted (see figure 118 and figure 119). the si signal is output from the selected slave and the so signal is the output from the master. the at8xc51snd1c captures data from the si line while the selected slave captures data from the so line. for simplicity, figure 118 and figure 119 depict the spi waveforms in idealized form and do not provide precise timing information. for timing parameters refer to the section ?ac characteristics?. note: 1. when the peripheral is disabled (spen = 0), default sck line is high level. figure 118. data transmission format (cpha = 0) spr2 spr1 spr0 bit rate (khz) vs f per f per divider 6 mhz (1) 8 mhz (1) 10 mhz (1) 12 mhz (2) 16 mhz (2) 20 mhz (2) 0 0 0 3000 4000 5000 6000 8000 10000 2 0 0 1 1500 2000 2500 3000 4000 5000 4 0 1 0 750 1000 1250 1500 2000 2500 8 0 1 1 375 500 625 750 1000 1250 16 1 0 0 187.5 250 312.5 375 500 625 32 1 0 1 93.75 125 156.25 187.5 250 312.5 64 1 1 0 46.875 62.5 78.125 93.75 125 156.25 128 1 1 1 6000 8000 10000 12000 16000 20000 1 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) capture point
153 at8xc51snd1c 4109h?8051?01/05 figure 119. data transmission format (cpha = 1) 20.2.2 ss management figure 118 shows an spi transmission with cpha = 0, where the first sck edge is the msb capture point. therefore the slave starts to output its msb as soon as it is selected: ss asserted to low level. ss must then be deasserted between each byte transmission (see figure 120). spdat must be loaded with a data before ss is asserted again. figure 119 shows an spi transmission with cpha = 1, where the first sck edge is used by the slave as a start of transmission signal. therefore, ss may remain asserted between each byte transmission (see figure 120). figure 120. ss timing diagram 20.2.3 error conditions the following flags signal the spi error conditions: modf in spsta signals a mode fault. modf flag is relevant only in master mode when ss usage is enabled (ssdis bit cleared). it signals when set that an other master on the bus has asserted ss pin and so, may create a conflict on the bus with 2 master sending data at the same time. a mode fault automatically disables the spi (spen cleared) and configures the spi in slave mode (mstr cleared). modf flag can trigger an interrupt as explained in section "interrupt", page 154. modf flag is cleared by reading spsta and re-configuring spi by writing to spcon. wcol in spsta signals a write collision. wcol flag is set when spdat is loaded while a transfer is on-going. in this case data is not written to spdat and transfer continue uninterrupted. wcol flag does not trigger any interrupt and is relevant jointly with spif flag. wcol flag is cleared after reading spsta and writing new data to spdat while no transfer is on-going. 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) capture point ss (cpha = 1) ss (cpha = 0) si/so byte 1 byte 2 byte 3
154 at8xc51snd1c 4109h?8051?01/05 20.3 interrupt the spi handles 2 interrupt sources that are the ?end of transfer? and the ?mode fault? flags. as shown in figure 121, these flags are combined toghether to appear as a single inter- rupt source for the c51 core. the spif flag is set at the end of an 8-bit shift in and out and is cleared by reading spsta and then reading from or writing to spdat. the modf flag is set in case of mode fault error and is cleared by reading spsta and then writing to spcon. the spi interrupt is enabled by setting espi bit in ien1 register. this assumes inter- rupts are globally enabled by setting ea bit in ien0 register. figure 121. spi interrupt system espi ien1.2 spi controller interrupt request spif spsta.7 modf spsta.4
155 at8xc51snd1c 4109h?8051?01/05 20.4 configuration the spi configuration is made through spcon. 20.4.1 master configuration the spi operates in master mode when the mstr bit in spcon is set. 20.4.2 slave configuration the spi operates in slave mode when the mstr bit in spcon is cleared and data has been loaded is spdat. 20.4.3 data exchange there are 2 possible methods to exchange data in master and slave modes: polling interrupts 20.4.4 master mode with polling policy figure 122 shows the initialization phase and the transfer phase flows using the polling method. using this flow prevents any overrun error occurrence. the bit rate is selected according to table 2. the transfer format depends on the slave peripheral. ss may be deasserted between transfers depending also on the slave peripheral. spif flag is cleared when reading spdat (spsta has been read before by the ?end of transfer? check). this polling method provides the fastest effective transmission and is well adapted when communicating at high speed with other microcontrollers. however, the procedure may then be interrupted at any time by higher priority tasks. figure 122. master spi polling flows spi initialization polling policy disable interrupt spie = 0 spi transfer polling policy end of transfer? spif = 1? select master mode mstr = 1 select bit rate program spr2:0 select format program cpol & cpha enable spi spen = 1 select slave pn.x = l start transfer write data in spdat last transfer? get data received read spdat deselect slave pn.x = h
156 at8xc51snd1c 4109h?8051?01/05 20.4.5 master mode with interrupt figure 123 shows the initialization phase and the transfer phase flows using the inter- rupt. using this flow prevents any overrun error occurrence. the bit rate is selected according to table 2. the transfer format depends on the slave peripheral. ss may be deasserted between transfers depending also on the slave peripheral. reading spsta at the beginning of the isr is mandatory for clearing the spif flag. clear is effective when reading spdat. figure 123. master spi interrupt flows spi initialization interrupt policy enable interrupt espi =1 spi interrupt service routine select master mode mstr = 1 select bit rate program spr2:0 select format program cpol & cpha enable spi spen = 1 read status read spsta start new transfer write data in spdat last transfer? get data received read spdat disable interrupt spie = 0 select slave pn.x = l start transfer write data in spdat deselect slave pn.x = h
157 at8xc51snd1c 4109h?8051?01/05 20.4.6 slave mode with polling policy figure 124 shows the initialization phase and the transfer phase flows using the polling. the transfer format depends on the master controller. spif flag is cleared when reading spdat (spsta has been read before by the ?end of reception? check). this provides the fastest effective transmission and is well adapted when communicat- ing at high speed with other microcontrollers. however, the process may then be interrupted at any time by higher priority tasks. figure 124. slave spi polling flows spi initialization polling policy disable interrupt spie = 0 spi transfer polling policy data received? spif = 1? select slave mode mstr = 0 select format program cpol & cpha enable spi spen = 1 prepare next transfer write data in spdat get data received read spdat prepare transfer write data in spdat
158 at8xc51snd1c 4109h?8051?01/05 20.4.7 slave mode with interrupt policy figure 123 shows the initialization phase and the transfer phase flows using the interrupt. the transfer format depends on the master controller. reading spsta at the beginning of the isr is mandatory for clearing the spif flag. clear is effective when reading spdat. figure 125. slave spi interrupt policy flows spi initialization interrupt policy enable interrupt espi =1 spi interrupt service routine select slave mode mstr = 0 select format program cpol & cpha enable spi spen = 1 get status read spsta prepare new transfer write data in spdat get data received read spdat prepare transfer write data in spdat
159 at8xc51snd1c 4109h?8051?01/05 20.5 registers table 6. spcon register spcon (s:c3h) ? spi control register reset value = 0001 0100b note: 1. when the spi is disabled, sck outputs high level. 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7spr2 spi rate bit 2 refer to table 2 for bit rate description. 6spen spi enable bit set to enable the spi interface. clear to disable the spi interface. 5ssdis slave select input disable bit set to disable ss in both master and slave modes . in slave mode this bit has no effect if cpha = 0. clear to enable ss in both master and slave modes. 4mstr master mode select set to select the master mode. clear to select the slave mode. 3cpol spi clock polarity bit (1) set to have the clock output set to high level in idle state. clear to have the clock output set to low level in idle state. 2cpha spi clock phase bit set to have the data sampled when the clock returns to idle state (see cpol). clear to have the data sampled when the clock leaves the idle state (see cpol). 1 - 0 spr1:0 spi rate bits 0 and 1 refer to table 2 for bit rate description.
160 at8xc51snd1c 4109h?8051?01/05 table 7. spsta register spsta (s:c4h) ? spi status register reset value = 00000 0000b table 8. spdat register spdat (s:c5h) ? synchronous serial data register reset value = xxxx xxxxb 76543210 spifwcol-modf---- bit number bit mnemonic description 7spif spi interrupt flag set by hardware when an 8-bit shift is completed. cleared by hardware when reading or writing spdat after reading spsta. 6wcol write collision flag set by hardware to indicate that a collision has been detected. cleared by hardware to indicate that no collision has been detected. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4modf mode fault set by hardware to indicate that the ss pin is at an appropriate level. cleared by hardware to indicate that the ss pin is at an inappropriate level. 3 - 0 - reserved the value read from these bits is indeterminate. do not set these bits. 76543210 spd7spd6spd5spd4spd3spd2spd1spd0 bit number bit mnemonic description 7 - 0 spd7:0 synchronous serial data.
161 at8xc51snd1c 4109h?8051?01/05 21. two-wire interface (twi) controller the at8xc51snd1c implements a twi controller supporting the four standard master and slave modes with multimaster capability. thus, it allows connection of slave devices like lcd controller, audio dac, etc., but also external master controlling where the at8xc51snd1c is used as a peripheral of a host. the twi bus is a bi-directional twi serial communication standard. it is designed prima- rily for simple but efficient integrated circuit control. the system is comprised of 2 lines, scl (serial clock) and sda (serial data) that carry information between the ics con- nected to them. the serial data transfer is limited to 100 kbit/s in low speed mode, however, some higher bit rates can be achieved depending on the oscillator frequency. various communication configurations can be designed using this bus. figure 126 shows a typical twi bus configuration us ing the at8xc51snd1c in master and slave modes. all the devices connected to the bus can be master and slave. figure 126. typical twi bus configuration 21.1 description the cpu interfaces to the twi logic via the following four 8-bit special function regis- ters: the synchronous serial control register (sscon sfr, see table 10), the synchronous serial data register (ssdat sfr, see table 12), the synchronous serial status register (sssta sfr, see table 11) and the synchronous serial address regis- ter (ssadr sfr, see table 13). sscon is used to enable the controller, to program the bit rate (see table 10), to enable slave modes, to acknowledge or not a received data, to send a start or a stop condition on the twi bus, and to acknowledge a serial interrupt. a hardware reset disables the twi controller. sssta contains a status code which reflects the status of the twi logic and the twi bus. the three least significant bits are always zero. the five most significant bits con- tains the status code. there are 26 possible status codes. when sssta contains f8h, no relevant state information is available and no serial interrupt is requested. a valid sta- tus code is available in sssta after ssi is set by hardware and is still present until ssi has been reset by software. table 3 to table 131 give the status for both master and slave modes and miscellaneous states. ssdat contains a byte of serial data to be transmitted or a byte which has just been received. it is addressable while it is not in process of shifting a byte. this occurs when twi logic is in a defined state and the serial interrupt flag is set. data in ssdat remains stable as long as ssi is set. while data is being shifted out, data on the bus is simulta- neously shifted in; ssdat always contains the last byte present on the bus. ssadr may be loaded with the 7 - bit slave addr ess (7 most significant bits) to which the controller will respond when programmed as a slave transmitter or receiver. the lsb is used to enable general call address (00h) recognition. figure 127 shows how a data transfer is accomplished on the twi bus. at8xc51snd1c master/slave lcd display audio dac p1.6/scl p1.7/sda rp rp host microprocessor scl sda
162 at8xc51snd1c 4109h?8051?01/05 figure 127. complete data transfer on twi bus the four operating modes are: master transmitter master receiver slave transmitter slave receiver data transfer in each mode of operation are shown in figure 128 through figure 131. these figures contain the following abbreviations: a acknowledge bit (low level at sda) a not acknowledge bit (high level on sda) data 8-bit data byte s start condition p stop condition mr master receive mt master transmit sla slave address gca general call address (00h) r read bit (high level at sda) w write bit (low level at sda) in figure 128 through figure 131, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in sssta. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when the serial interrupt routine is entered, the status code in sssta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in table 3 through table 131. s slave address scl sda msb r/w direction ack signal nth data byte ack signal p/s bit from receiver from receiver 12 89 12 89 clock line held low while serial interrupts are serviced
163 at8xc51snd1c 4109h?8051?01/05 21.1.1 bit rate the bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the sscr2, sscr1, and sscr0 control bits in sscon (see table 10). the predefined bit rates are derived from the peripheral clock (f per ) issued from the clock controller block as detailed in section "oscillator", page 12, while bit rate generator is based on timer 1 overflow output. note: 1. these bit rates are outside of the low speed standard specification limited to 100 khz but can be used with high speed twi components limited to 400 khz. 21.2.1 master transmitter mode in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 128). before the master transmitter mode can be entered, sscon must be initialized as follows: sscr2:0 define the serial bit rate (see table 2). sspe must be set to enable the con- troller. sssta, sssto and ssi must be cleared. the master transmitter mode may now be entered by setting the sssta bit. the twi logic will now monitor the twi bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (ssi bit in sscon) is set, and the status code in sssta is 08h. this status must be used to vector to an interrupt routine that loads ssdat with the slave address and the data direction bit (sla+w). the serial interrupt flag (ssi) must then be cleared before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowl- edgment bit has been received, ssi is set again and a number of status code in sssta are possible. there are 18h, 20h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (ssaa = logic 1). the appropriate action to be taken for each of these status code is detailed in table 3. this scheme is repeated until a stop condition is transmitted. sspe and sscr2:0 are not affected by the serial transfer and are not referred to in table 3. after a repeated start condition (state 10h) the controller may switch to the master receiver mode by loading ssdat with sla+r. table 2. serial clock rates sscrx bit frequency (khz) f per divided by 210 f per = 6 mhz f per = 8 mhz f per = 10 mhz 0 0 0 47 62.5 78.125 128 0 0 1 53.5 71.5 89.3 112 0 1 0 62.5 83 104.2 (1) 96 0 1 1 75 100 125 (1) 80 1 0 0 12.5 16.5 20.83 480 1 0 1 100 133.3 (1) 166.7 (1) 60 110 200 (1) 266.7 (1) 333.3 (1) 30 1 1 1 0.5 < ? < 125 (1) 0.67 < ? < 166.7 (1) 0.81 < ? < 208.3 (1) 96 ? (256 ? reload value timer 1) sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 bit rate1000xbit ratebit rate
164 at8xc51snd1c 4109h?8051?01/05 21.2.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmit- ter (see figure 129). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt routine must load ssdat with the 7 - bit slave address and the data direction bit (sla+r). the serial interrupt flag (ssi) must then be cleared before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowl- edgment bit has been received, the serial interrupt flag is set again and a number of status code in sssta are possible. there are 40h, 48h or 38h for the master mode and also 68h, 78h or b0h if the slave mode was enabled (ssaa = logic 1). the appropriate action to be taken for each of these status code is detailed in table 131. this scheme is repeated until a stop condition is transmitted. sspe and sscr2:0 are not affected by the serial transfer and are not referred to in table 131. after a repeated start condition (state 10h) the controller may switch to the master transmitter mode by loading ssdat with sla+w. 21.2.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmit- ter (see figure 130). to initiate the slave receiver mode, ssadr and sscon must be loaded as follows: the upper 7 bits are the addresses to which the controller will respond when addressed by a master. if the lsb (ssgc) is set, t he controller will respond to the general call address (00h); otherwise, it ignores the general call address. sscr2:0 have no effect in the slave mode. sspe must be set to enable the controller. the ssaa bit must be set to enable the own slave address or the general call address acknowledgment. sssta, sssto and ssi must be cleared. when ssadr and sscon have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 0 (w) for operating in the slave receiver mode. after its own slave address and the w bit has been received, the serial interrupt flag is set and a valid status code can be read from sssta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in table 131 and table 7. the slave receiver mode may also be entered if arbitration is lost while the controller is in the master mode (see states 68h and 78h). if the ssaa bit is reset during a transfer, the controller will return a not acknowledge (logic 1) to sda after the next received data byte. while ssaa is reset, the controller does not respond to its own slave address. however, the twi bus is still monitored and address recognition may be resumed at any time by setting ssaa. this means that the ssaa bit may be used to temporarily isolate the controller from the twi bus. ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 ssgc ?????????? own slave address ?????????? x sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 x10001xx
165 at8xc51snd1c 4109h?8051?01/05 21.2.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 131). data transfer is initialized as in the slave receiver mode. when ssadr and sscon have been initialized, the controller waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (r) for operating in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag is set and a valid status code can be read from sssta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in table 7. the slave transmitter mode may also be entered if arbitration is lost while the controller is in the master mode (see state b0h). if the ssaa bit is reset during a transfer, the controller will transmit the last byte of the transfer and enter state c0h or c8h. the controller is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the mas- ter receiver receives all 1?s as serial data. while ssaa is reset, the controller does not respond to its own slave address. however, the twi bus is still monitored and address recognition may be resumed at any time by setting ssaa. this means that the ssaa bit may be used to temporarily isolate the controller from the twi bus. 21.2.5 miscellaneous states there are 2 sssta codes that do not correspond to a defined twi hardware state (see table 8). these are discussed below. status f8h indicates that no relevant information is available because the serial interrupt flag is not yet set. this occurs between other states and when the controller is not involved in a serial transfer. status 00h indicates that a bus error has occurred during a serial transfer. a bus error is caused when a start or a stop condition occu rs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, ssi is set. to recover from a bus error, the sssto flag must be set and ssi must be cleared. this causes the controller to enter the not addressed slave mode and to clear the sssto flag (no other bits in s1con are affected). the sda and scl lines are released and no stop condition is transmitted. note: the twi controller interfaces to the external twi bus via 2 port 1 pins: p1.6/scl (serial clock line) and p1.7/sda (serial data line). to avoid low level asserting and conflict on these lines when the twi controller is enabled, the output latches of p1.6 and p1.7 must be set to logic 1.
166 at8xc51snd1c 4109h?8051?01/05 figure 128. format and states in the master transmitter mode data 20h a sla 08h mt m r successful transmis- sion to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave not acknowledge received data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sw 18h a p 28h sla sw r a p 10h 30h a p 38h a or a continues other master 38h a or a continues other master 68h a continues other master 78h b0h nnh after a data byte to corresponding states in slave mode
167 at8xc51snd1c 4109h?8051?01/05 figure 129. format and states in the master receiver mode a data 48h a sla 08h mr mt successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sr 40h a p 58h sla sr w a p 10h 38h a continues other master 38h a or a continues other master 68h a continues other master 78h b0h nnh to corresponding states in slave mode data 50h
168 at8xc51snd1c 4109h?8051?01/05 figure 130. format and states in the slave receiver mode a data 68h a sla reception of the own slave address and one or more last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes arbitration lost as master and addressed as slave by general call data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sw 60h a p or s 80h a nnh data 80h a0h 88h a p or s a data 78h a general call 70h a p or s 90h a data 90h a0h 98h a p or s data bytes. all are acknowledged last data byte received is not acknowledged
169 at8xc51snd1c 4109h?8051?01/05 figure 131. format and states in the slave transmitter mode a data b0h a sla data a from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in sssta) corresponds to a defined state of the twi bus sr a8h a p or s c0h all 1?s ap or s c8h nnh data b8h a arbitration lost as master and addressed as slave reception of the own slave address and transmission of one or more data bytes. last data byte transmitted. switched to not addressed slave (ssaa = 0).
170 at8xc51snd1c 4109h?8051?01/05 table 3. status for master transmitter mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+w x00x sla+w will be transmitted. 10h a repeated start condition has been transmitted write sla+w write sla+r x x 0 0 0 0 x x sla+w will be transmitted. sla+r will be transmitted. logic will switch to master receiver mode 18h sla+w has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 20h sla+w has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 28h data byte has been transmitted; ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 30h data byte has been transmitted; not ack has been received write data byte no ssdat action no ssdat action no ssdat action 0 1 0 1 0 0 1 1 0 0 0 0 x x x x data byte will be transmitted. repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 38h arbitration lost in sla+w or data bytes no ssdat action no ssdat action 0 1 0 0 0 0 x x twi bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free.
171 at8xc51snd1c 4109h?8051?01/05 table 4. status for master receiver mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 08h a start condition has been transmitted write sla+r x00x sla+r will be transmitted. 10h a repeated start condition has been transmitted write sla+r write sla+w x x 0 0 0 0 x x sla+r will be transmitted. sla+w will be transmitted. logic will switch to master transmitter mode. 38h arbitration lost in sla+r or not ack bit no ssdat action no ssdat action 0 1 0 0 0 0 x x twi bus will be released and not addressed slave mode will be entered. a start condition will be transmitted when the bus becomes free. 40h sla+r has been transmitted; ack has been received no ssdat action no ssdat action 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 48h sla+r has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset. 50h data byte has been received; ack has been returned read data byte read data byte 0 0 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 58h data byte has been received; not ack has been returned read data byte read data byte read data byte 1 0 1 0 1 1 0 0 0 x x x repeated start will be transmitted. stop condition will be transmitted and sssto flag will be reset. stop condition followed by a start condition will be transmitted and sssto flag will be reset.
172 at8xc51snd1c 4109h?8051?01/05 table 5. status for slave receiver mode with own slave address status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 60h own sla+w has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 80h previously addressed with own sla+w; data has been received; ack has been returned read data byte read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 88h previously addressed with own sla+w; data has been received; not ack has been returned read data byte read data byte read data byte read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free.
173 at8xc51snd1c 4109h?8051?01/05 table 6. status for slave receiver mode with general call address status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa 70h general call address has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 78h arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no ssdat action no ssdat action x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 90h previously addressed with general call; data has been received; ack has been returned read data byte read data byte x x 0 0 0 0 0 1 data byte will be received and not ack will be returned. data byte will be received and ack will be returned. 98h previously addressed with general call; data has been received; not ack has been returned read data byte read data byte read data byte read data byte 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start condition has been received while still addressed as slave no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free.
174 at8xc51snd1c 4109h?8051?01/05 table 7. status for slave transmitter mode status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa a8h own sla+r has been received; ack has been returned write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. b8h data byte in ssdat has been transmitted; ack has been received write data byte write data byte x x 0 0 0 0 0 1 last data byte will be transmitted. data byte will be transmitted. c0h data byte in ssdat has been transmitted; not ack has been received no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in ssdat has been transmitted (ssaa= 0); ack has been received no ssdat action no ssdat action no ssdat action no ssdat action 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. switched to the not addressed slave mode; no recognition of own sla or gca. a start condition will be transmitted when the bus becomes free. switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if ssgc = logic 1. a start condition will be transmitted when the bus becomes free. table 8. status for miscellaneous states status code sssta status of the twi bus and twi hardware application software response next action taken by twi hardware to/from ssdat to sscon sssta sssto ssi ssaa f8h no relevant state information available; ssi = 0 no ssdat action no sscon action wait or proceed current transfer. 00h bus error due to an illegal start or stop condition no ssdat action 010x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and sssto is reset.
175 at8xc51snd1c 4109h?8051?01/05 21.9 registers table 10. sscon register sscon (s:93h) ? synchronous serial control register reset value = 0000 0000b 76543210 sscr2 sspe sssta sssto ssi ssaa sscr1 sscr0 bit number bit mnemonic description 7 sscr2 synchronous serial control rate bit 2 refer to table 2 for rate description. 6sspe synchronous serial peripheral enable bit set to enable the controller. clear to disable the controller. 5sssta synchronous serial start flag set to send a start condition on the bus. clear not to send a start condition on the bus. 4sssto synchronous serial stop flag set to send a stop condition on the bus. clear not to send a stop condition on the bus. 3ssi synchronous serial interrupt flag set by hardware when a serial interrupt is requested. must be cleared by software to acknowledge interrupt. 2ssaa synchronous serial assert acknowledge flag set to enable slave modes. slave modes are entered when sla or gca (if ssgc set) is recognized. clear to disable slave modes. master receiver mode in progress clear to force a not acknowledge (high level on sda). set to force an acknowledge (low level on sda). master transmitter mode in progress this bit has no specific effect when in master transmitter mode. slave receiver mode in progress clear to force a not acknowledge (high level on sda). set to force an acknowledge (low level on sda). slave transmitter mode in progress clear to isolate slave from the bus after last data byte transmission. set to enable slave mode. 1 sscr1 synchronous serial control rate bit 1 refer to table 2 for rate description. 0 sscr0 synchronous serial control rate bit 0 refer to table 2 for rate description.
176 at8xc51snd1c 4109h?8051?01/05 table 11. sssta register sssta (s:94h) ? synchronous serial status register reset value = f8h table 12. ssdat register ssdat (s:95h) ? synchronous serial data register reset value = 1111 1111b table 13. ssadr register ssadr (s:96h) ? synchronous serial address register reset value = 1111 1110b 76543210 ssc4 ssc3 ssc2 ssc1 ssc0 0 0 0 bit number bit mnemonic description 7:3 ssc4:0 synchronous serial status code bits 0 to 4 refer to table 3 to table 131 for status description. 2:0 0 always 0. 76543210 ssd7 ssd6 ssd5 ssd4 ssd3 ssd2 ssd1 ssd0 bit number bit mnemonic description 7:1 ssd7:1 synchronous serial address bits 7 to 1 or synchronous serial data bits 7 to 1 0 ssd0 synchronous serial address bit 0 (r/w) or synchronous serial data bit 0 76543210 ssa7ssa6ssa5ssa4ssa3ssa2ssa1ssgc bit number bit mnemonic description 7:1 ssa7:1 synchronous serial slave address bits 7 to 1 0ssgc synchronous serial general call bit set to enable the general call address recognition. clear to disable the general call address recognition.
177 at8xc51snd1c 4109h?8051?01/05 22. analog to digital converter the at8xc51snd1c implement a 2-channel 10-bit (8 true bits) analog to digital con- verter (adc). first channel of this adc c an be used for battery monitoring while the second one can be used for voice sampling at 8 khz. 22.1 description the a/d converter interfaces with the c51 core through four special function registers: adcon, the adc control register (see table 4); addh and addl, the adc data regis- ters (see table 6 and table 7); and adclk, the adc clock register (see table 5). as shown in figure 132, the adc is composed of a 10-bit cascaded potentiometric digi- tal to analog converter, connected to the negative input of a comparator. the output voltage of this dac is compared to the analog voltage stored in the sample and hold and coming from ain0 or ain1 input depending on the channel selected (see table 2). the 10-bit addat converted value (see formula in figure 132) is delivered in addh and addl registers, addh is giving the 8 most significant bits while addl is giving the 2 least significant bits. addat figure 132. adc structure figure 133 shows the timing diagram of a complete conversion. for simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. for adc characteristics and timing parameters refer to the section ?ac characteristics?. figure 133. timing diagram 0 1 ain1 ain0 adcs adcon.0 avss sample and hold addh arefp r/2r dac adc clock arefn 8 10 aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrup t reques t eadc ien1.3 control + - addl 2 sar addat 1023 v ? in v ref --------------------------- = aden adsst adeoc t setup t conv clk t adclk
178 at8xc51snd1c 4109h?8051?01/05 22.1.1 clock generator the adc clock is generated by division of the peripheral clock (see details in section ?x2 feature?, page 12). the division fa ctor is then given by adcp4:0 bits in adclk register. figure 134 shows the adc clock generator and its calculation formula (1) . figure 134. adc clock generator and symbol caution: note: 1. in all cases, the adc clock frequency may be higher than the maximum f adclk parameter reported in the section ?analog to digital converter?, page 202. 2. the adcd value of 0 is equivalent to an adcd value of 32. 22.1.2 channel selection the channel on which conversion is perfor med is selected by the adcs bit in adcon register according to table 2. table 2. adc channel selection 22.2.1 conversion precision the 10-bit precision conversion is achieved by stopping the cpu core activity during conversion for limiting the digital noise i nduced by the core. this mode called the pseudo-idle mode (1),(2) is enabled by setting the adidl bit in adcon register (3) . thus, when conversion is launched (see section "conversion launching", page 179), the cpu core is stopped until the end of the conversion (see section "end of conversion", page 179). this bit is cleared by hardware at the end of the conversion. notes: 1. only the cpu activity is frozen, peripherals are not affected by the pseudo-idle mode. 2. if some interrupts occur during the pseudo-idle mode, they will be delayed and pro- cessed, according to their priority after the end of the conversion. 3. concurrently with adsst bit. 22.2.2 configuration the adc configuration consists in programming the adc clock as detailed in the sec- tion "clock generator", page 178. the adc is enabled using the aden bit in adcon register. as shown in figure 93, user must wait the setup time (t setup ) before launching any conversion. adcd4:0 adclk adc clock adcclk perclk 2adcd ? ------------------------- = adc clock symbo l adc clock per clock 2 adcs channel 0ain1 1ain0
179 at8xc51snd1c 4109h?8051?01/05 figure 135. adc configuration flow 22.2.3 conversion launching the conversion is launched by setting the adsst bit in adcon register, this bit remains set during the conversion. as soon as the conversion is started, it takes 11 clock periods (t conv ) before the data is available in addh and addl registers. figure 136. adc conversion launching flow 22.2.4 end of conversion the end of conversion is signalled by the adeoc flag in adcon register becoming set or by the adsst bit in adcon register becoming cleared. adeoc flag can generate an interrupt if enabled by setting eadc bit in ien1 register. this flag is set by hardware and must be reset by software. adc configuration enable adc adidl = x aden = 1 wait setup time program adc clock adcd4:0 = xxxxxb adc conversion start select channel adcs = 0-1 start conversion adsst = 1
180 at8xc51snd1c 4109h?8051?01/05 22.3 registers table 4. adcon register adcon (s:f3h) ? adc control register reset value = 0000 0000b table 5. adclk register adclk (s:f2h) ? adc clock divider register reset value = 0000 0000b 76543210 - adidl aden adeoc adsst - - adcs bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6adidl adc pseudo-idle mode set to suspend the cpu core activity (pseudo-idle mode) during conversion. clear by hardware at the end of conversion. 5aden adc enable bit set to enable the a to d converter. clear to disable the a to d converte r and put it in low power stand by mode. 4adeoc end of conversion flag set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3 adsst start and status bit set to start an a to d conversion on the selected channel. cleared by hardware at the end of conversion. 2 - 1 - reserved the value read from these bits is always 0. do not set these bits. 0 adcs channel selection bit set to select channel 0 for conversion. clear to select channel 1 for conversion. 76543210 - - - adcd4 adcd3 adcd2 adcd1 adcd0 bit number bit mnemonic description 7 - 5 - reserved the value read from these bits is always 0. do not set these bits. 4 - 0 adcd4:0 adc clock divider 5-bit divider for adc clock generation.
181 at8xc51snd1c 4109h?8051?01/05 table 6. addh register addh (s:f5h read only) ? adc data high byte register reset value = 0000 0000b table 7. addl register addl (s:f4h read only) ? adc data low byte register reset value = 0000 0000b 76543210 adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2 bit number bit mnemonic description 7 - 0 adat9:2 adc data 8 most significant bits of the 10-bit adc data. 76543210 ------adat1adat0 bit number bit mnemonic description 7 - 2 - reserved the value read from these bits is always 0. do not set these bits. 1 - 0 adat1:0 adc data 2 least significant bits of the 10-bit adc data.
182 at8xc51snd1c 4109h?8051?01/05 23. keyboard interface the at8xc51snd1c implement a keyboard interface allowing the connection of a 4 x n matrix keyboard. it is based on 4 inputs with programmable interrupt capability on both high or low level. these inputs are available as alternate function of p1.3:0 and allow exit from idle and power down modes. 23.1 description the keyboard interfaces with the c51 core through 2 special function registers: kbcon, the keyboard control register (see table 3 ); and kbsta, the keyboard control and sta- tus register (see table 4). the keyboard inputs are considered as 4 independent interrupt sources sharing the same interrupt vector. an interrupt enable bit (ekb in ien1 register) allows global enable or disable of the keyboard interrupt (see figure 137). as detailed in figure 138 each keyboard input has the capability to detect a programmable level according to kinl3:0 bit value in kbcon register. level detection is then reported in interrupt flags kinf3:0 in kbsta register. a keyboard interrupt is requested each time one of the four flags is set, i.e. the input level matches the programmed one. each of these four flags can be masked by soft- ware using kinm3:0 bits in kbcon register and is cleared by reading kbsta register. this structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow usage of kin inputs for any other purposes. figure 137. keyboard interface block diagram figure 138. keyboard input circuitry 23.1.1 power reduction mode kin3:0 inputs allow exit from idle and power-down modes as detailed in section ?power management?, page 48. to enable this feature, kpde bit in kbsta register must be set to logic 1. due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit may happen on parasitic key press. in this case, no key is detected and software must enter power down again. kin0 keyboard interfac e interrupt request ekb ien1.4 input circuitry kin1 input circuitry kin2 input circuitry kin3 input circuitry kin3:0 kinm3:0 kbcon.3:0 kinf3:0 kbsta.3:0 kinl3:0 kbcon.7:4 0 1
183 at8xc51snd1c 4109h?8051?01/05 23.2 registers table 3. kbcon register kbcon (s:a3h) ? keyboard control register reset value = 0000 1111b table 4. kbsta register kbsta (s:a4h) ? keyboard control and status register reset value = 0000 0000b 76543210 kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 bit number bit mnemonic description 7 - 4 kinl3:0 keyboard input level bit set to enable a high level detection on the respective kin3:0 input. clear to enable a low level detection on the respective kin3:0 input. 3 - 0 kinm3:0 keyboard input mask bit set to prevent the respective kinf3:0 flag from generating a keyboard interrupt. clear to allow the respective kinf3: 0 flag to generate a keyboard interrupt. 76543210 kpde - - - kinf3 kinf2 kinf1 kinf0 bit number bit mnemonic description 7kpde keyboard power down enable bit set to enable exit of power down mode by the keyboard interrupt. clear to disable exit of power down mode by the keyboard interrupt. 6 - 4 - reserved the value read from these bits is always 0. do not set these bits. 3 - 0 kinf3:0 keyboard input interrupt flag set by hardware when the respective ki n3:0 input detects a programmed level. cleared when reading kbsta.
184 at8xc51snd1c 4109h?8051?01/05 24. electrical characteristics 24.1 absolute maximum rating 24.2 dc characteristics 24.2.1 digital logic storage temperature ......................................... -65 to +150 c voltage on any other pin to v ss .................................... -0.3 to +4.0 v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w operating conditions ambient temperature under bias........................ -40 to +85 c v dd ........................................................................................................................ 4.0v *notice: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 3. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2v dd -0.1 v v ih1 (2) input high voltage (except rst, x1) 0.2v dd +1.1 v dd v v ih2 input high voltage (rst, x1) 0.7v dd v dd +0.5 v v ol1 output low voltage (except p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 1.6 ma v ol2 output low voltage (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 3.2 ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd -0.7 v i oh = -30 a v oh2 output high voltage (p0, p2 address mode, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd -0.7 v i oh = -3.2 ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 av in = 0.45 v i li input leakage current (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a 0.45< v in < v dd i tl logical 1 to 0 transition current (p1, p2, p3, p4 and p5) -650 av in = 2.0 v r rst pull-down resistor 50 90 200 k ? c io pin capacitance 10 pf t a = 25 c v ret v dd data retention limit 1.8 v
185 at8xc51snd1c 4109h?8051?01/05 notes: 1. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is no guarantee on these values. 2. flash retention is guaranteed with the same formula for v dd min down to 0v. 3. see table 4 for typical consumption in player mode. table 4. typical reference design at89c51snd1c power consumption i dd at89c51snd1c operating current (3) x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at83snd1c operating current x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at80c51snd1c idle mode current x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i dl at89c51snd1c idle mode current (3) x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at83snd1c idle mode current x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz at80c51snd1c idle mode current x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i pd at89c51snd1c power-down mode current 20 500 av ret < v dd < 3.3 v at83snd1c power-down mode current 20 500 av ret < v dd < 3.3 v at80c51snd1c power-down mode current 20 500 av ret < v dd < 3.3 v i fp at89c51snd1c flash programming current 15 ma v dd < 3.3 v table 3. digital dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ (1) max units test conditions player mode i dd test conditions stop 10 ma at89c51snd1c at 16 mhz, x2 mode, v dd = 3 v no song playing playing 30 ma at89c51snd1c at 16 mhz, x2 mode, v dd = 3 v mp3 song with fs= 44.1 khz, at any bit rates (variable bit rate)
186 at8xc51snd1c 4109h?8051?01/05 i dd, i dl and i pd test conditions figure 139. i dd test condition, active mode figure 140. i dl test condition, idle mode figure 141. i pd test condition, power-down mode rst tst p0 all other pins are unconnected vdd vdd vdd i dd vdd pvdd uvdd avdd x2 clock signal vss x1 (nc) vss pvss uvss avss x2 vdd clock signal rst vss tst x1 p0 (nc) i dl all other pins are unconnected vss vdd vss vdd pvdd uvdd avdd pvss uvss avss rst mcmd p0 all other pins are unconnected vss vdd tst mdat vdd i pd vdd pvdd uvdd avdd x2 vss x1 (nc) vss pvss uvss avss
187 at8xc51snd1c 4109h?8051?01/05 24.4.1 a to d converter table 5. a to d converter dc characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c 24.5.1 oscillator & crystal schematic figure 142. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in spe- cial cases (max 10 pf). x1 and x2 may not be used to drive other circuits. parameters table 6. oscillator & crystal characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter min typ max units test conditions av dd analog supply voltage 2.7 3.3 v ai dd analog operating supply current 600 a av dd = 3.3v ain1:0= 0 to av dd aden= 1 ai pd analog standby current 2 a av dd = 3.3v aden= 0 or pd= 1 av in analog input voltage av ss av dd v av ref reference voltage a refn a refp av ss 2.4 av dd v r ref aref input resistance 10 30 k ? t a = 25 c c ia analog input capacitance 10 pf t a = 25 c vss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - vss) 10 pf c x2 internal capacitance (x2 - vss) 10 pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 ? cs crystal shunt capacitance 6 pf
188 at8xc51snd1c 4109h?8051?01/05 24.6.1 phase lock loop schematic figure 143. pll filter connection parameters table 7. pll filter characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c 24.7.1 usb connection schematic figure 144. usb connection parameters table 8. usb termination characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c 24.8.1 in system programming schematic figure 145. isp pull-down connection parameters table 9. isp pull-down characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c vss filt r c1 c2 vss symbol parameter min typ max unit r filter resistor 100 ? c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf d+ d- vbus gnd d+ d- vss to power supply r usb r usb symbol parameter min typ max unit r usb usb termination resistor 27 ? vss isp r isp symbol parameter min typ max unit r isp isp pull-down resistor 2.2 k ?
189 at8xc51snd1c 4109hs?8051?01/05 24.10 ac characteristics 24.10.1 external program bus cycles definition of symbols table 11. external program bus cycles timing symbol definitions timings test conditions: capacitive load on all pins= 50 pf. table 12. external program bus cycle - read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c signals conditions a address h high i instruction in l low lale vvalid ppsen x no longer valid zfloating symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl - 20 ns t llax address hold after ale low t clcl -20 0.5t clcl - 20 ns t lliv ale low to valid instruction 4t clcl -35 2t clcl -35 ns t plph psen pulse width 3t clcl -25 1.5t clcl - 25 ns t pliv psen low to valid instruction 3t clcl -35 1.5t clcl - 35 ns t pxix instruction hold after psen high 0 0 ns t pxiz instruction float after psen high t clcl -10 0.5t clcl - 10 ns t aviv address valid to valid instruction 5t clcl -35 2.5t clcl - 35 ns t plaz psen low to address float 10 10 ns
190 at8xc51snd1c 4109hs?8051?01/05 waveforms figure 146. external program bus cycle - read waveforms 24.12.1 external data 8-bit bus cycles definition of symbols table 13. external data 8-bit bus cycles timing symbol definitions timings test conditions: capacitive load on all pins= 50 pf. table 14. external data 8-bit bus cycle - read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c t pliv p2 p0 psen ale t lhll t plph instruction in a15:8 t llpl a7:0 a15:8 t avll t llax t plaz d7:0 t pxix t pxiz d7:0 t pxav instruction in a7:0 d7:0 signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns
191 at8xc51snd1c 4109hs?8051?01/05 t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +2 0 ns t avdv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t av rl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max
192 at8xc51snd1c 4109hs?8051?01/05 table 15. external data 8-bit bus cycle - write ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c waveforms figure 147. external data 8-bit bus cycle - read waveforms symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +2 0 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in a15:8 t rlaz t llrl t rhlh t rldv d7:0 a7:0
193 at8xc51snd1c 4109hs?8051?01/05 figure 148. external data 8-bit bus cycle - write waveforms 24.15.1 external ide 16-bit bus cycles definition of symbols table 16. external ide 16-bit bus cycles timing symbol definitions t whlh t av wl t llax t whqx p2 p0 wr ale t lhll t wlwh a15:8 t avll t qvwh d7:0 data out t llwl a7:0 signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr
194 at8xc51snd1c 4109hs?8051?01/05 timings test conditions: capacitive load on all pins= 50 pf. table 17. external ide 16-bit bus cycle - data read ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c table 18. external ide 16-bit bus cycle - data write ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +2 0 ns t avdv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t av rl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +2 0 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns
195 at8xc51snd1c 4109hs?8051?01/05 waveforms figure 149. external ide 16-bit bus cycle - data read waveforms note: 1. d15:8 is written in dat16h sfr. figure 150. external ide 16-bit bus cycle - data write waveforms note: 1. d15:8 is the content of dat16h sfr. 24.19 spi interface definition of symbols table 20. spi interface timing symbol definitions t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in t rlaz t llrl t rhlh t rldv d7:0 a7:0 data in d15:8 (1) a15:8 t whlh t av wl t llax t whqx p2 p0 wr ale t lhll t wlwh t avll t qvwh d7:0 data out t llwl a7:0 d15:8 (1) data out a15:8 signals conditions c clock h high i data in l low o data out v valid x no longer valid zfloating
196 at8xc51snd1c 4109hs?8051?01/05 timings test conditions: capacitive load on all pins= 50 pf. table 21. spi interface master ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c note: 1. value of this parameter depends on software. symbol parameter min max unit slave mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t slch , t slcl ss low to clock edge 100 ns t ivcl , t ivch input data valid to clock edge 40 ns t clix , t chix input data hold after clock edge 40 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t slov ss low to output data valid 50 ns t shox output data hold after ss high 50 ns t shsl ss high to ss low (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t ivcl , t ivch input data valid to clock edge 20 ns t clix , t chix input data hold after clock edge 20 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
197 at8xc51snd1c 4109hs?8051?01/05 waveforms figure 151. spi slave waveforms (sscpha= 0) note: 1. not defined but generally the msb of the character which has just been received. figure 152. spi slave waveforms (sscpha= 1) note: 1. not defined but generally the lsb of the character which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch
198 at8xc51snd1c 4109hs?8051?01/05 figure 153. spi master waveforms (sscpha= 0) note: 1. ss handled by software using general purpose port pin. figure 154. spi master waveforms (sscpha= 1) note: 1. ss handled by software using general purpose port pin. mosi (input) sck (sscpol= 0) (output) ss (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch mosi (input) sck (sscpol= 0) (output) ss (1) (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
199 at8xc51snd1c 4109hs?8051?01/05 24.21.1 two-wire interface timings table 22. twi interface ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maximum capacitance on bus-lines sda and scl= 400 pf. 4. t clcl = t osc = one oscillator clock period. waveforms figure 155. two wire waveforms symbol parameter input m i n max output m i n max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high scl high time 14t clcl (4) 4.0 s (1) t rc scl rise time 1 s- (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) - t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) - t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s - (2) t fd sda fall time 0.3 s0.3 s (3) tsu ;d at 1 t su ;sta ts u ; d at 2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t hd; dat t su; dat3 start or repeated start condition start condition stop condition repeated start condition
200 at8xc51snd1c 4109hs?8051?01/05 24.22.1 mmc interface definition of symbols table 23. mmc interface timing symbol definitions timings table 24. mmc interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 100pf (10 cards) waveforms figure 156. mmc input-output waveforms signals conditions c clock h high d data in l low o data out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox
201 at8xc51snd1c 4109hs?8051?01/05 24.24.1 audio interface definition of symbols table 25. audio interface timing symbol definitions timings table 26. audio interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 30pf note: 1. 32-bit format with fs= 48 khz. waveforms figure 157. audio interface waveforms signals conditions c clock h high o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns d clk t chch t clcx t chcx t clch t chcl dsel d dat right left t clsv t clov
202 at8xc51snd1c 4109hs?8051?01/05 24.26.1 analog to digital converter definition of symbols table 27. analog to digital converter timing symbol definitions characteristics table 28. analog to digital converter ac characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. av dd = av refp = 3.0 v, av ss = av refn = 0 v. adc is monotonic with no missing code. 2. the differential non-linearity is the difference between the actual step width and the ideal step width (see figure 159). 3. the integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see figure 159). 4. the offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see figure 159). 5. the gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see figure 159). waveforms figure 158. analog to digital converter internal waveforms signals conditions c clock h high e enable (aden bit) l low s start conversion (adsst bit) symbol parameter min max unit t clcl clock period 4 s t ehsh start-up time 4 s t shsl conversion time 11t clcl s dle differential non- linearity error (1)(2) 1lsb ile integral non- linearity errorss (1)(3) 2lsb ose offset error (1)(4) 4lsb ge gain error (1)(5) 4lsb aden bit adsst bit t ehsh t shsl clk t clcl
203 at8xc51snd1c 4109hs?8051?01/05 figure 159. analog to digital converter characteristics 24.28.1 flash memory definition of symbols table 29. flash memory timing symbol definitions timings table 30. flash memory ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 offset error ose code out avin offset error ose gain error ge ideal transfer curve 1 lsb (ideal) integral non-linearity (ile) differential non-linearity (dle) center of a step example of an actual transfer curve 0 0 (lsb ideal) signals conditions sisp l low rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input isp valid to rst edge 50 ns t rlsx input isp hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms n fcy number of flash write cycles 100k cycle t fdr flash data retention time 10 years
204 at8xc51snd1c 4109hs?8051?01/05 waveforms figure 160. flash memory - isp waveforms note: 1. isp must be driven through a pull-down resistor (see section ?in system program- ming?, page 188). figure 161. flash memory - internal busy waveforms 24.30.1 external clock drive and logic level references definition of symbols table 31. external clock timing symbol definitions timings table 32. external clock ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c waveforms figure 162. external clock waveform rst t svrl isp (1) t rlsx fbusy bit t bhbl signals conditions c clock h high l low x no longer valid symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx
205 at8xc51snd1c 4109hs?8051?01/05 figure 163. ac testing input/output waveforms note: 1. during ac testing, all inputs are driven at v dd -0.5 v for a logic 1 and 0.45 v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 164. float waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. 0.45 v v dd - 0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh - 0.1 v v ol + 0.1 v v load + 0.1 v v load - 0.1 v timing reference points
206 at8xc51snd1c 4109hs?8051?01/05 25. ordering information notes: 1. refers to rom code. 2. plcc84 package only available for development board. part number memory size supply voltage temperature range max frequency package (2) packing product marking at89c51snd1c-rotil 64k flash 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at89c51snd1c-7htil 64k flash 3v industrial 40 mhz bga81 tray 89c51snd1c-il at89c51snd1c-ddv 64k flash 3v industrial 40 mhz dice tray - at83snd1cxxx (1) -rotil 64k rom 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at83snd1cxxx (1) -7htil 64k rom 3v industrial 40 mhz bga81 tray 89c51snd1c-il at83snd1cxxx-ddv 64k rom 3v industrial 40 mhz dice tray - at80c51snd1c-rotil romless 3v industrial 40 mhz tqfp80 tray 89c51snd1c-il at80c51snd1c-7htil romless 3v industrial 40 mhz bga81 tray 89c51snd1c-il at80c51snd1c-ddv romless 3v industrial 40 mhz dice tray -
207 at8xc51snd1c 4109h?8051?01/05 26. package information 26.1 tqfp80
208 at8xc51snd1c 4109h?8051?01/05 26.2 bga81
209 at8xc51snd1c 4109h?8051?01/05 26.3 plcc84
210 at8xc51snd1c 4109h?8051?01/05 27. datasheet change log for at8xc51snd1c 27.1 changes from 4109d-10/02 to 4109e- 06/03 1. additional information on at83snd1c product. 2. added bga81 package. 3. updated ac/dc characteristics for at89c51snd1c product. 4. changed the endurance of flash to 100, 000 write/erase cycles. 5. added note on flash retention formula for v ih1 , in section "dc characteristics", page 184. 27.2 changes from 4109e-06/03 to 4109f- 01/04 1. added at80c51snd1c romless product. 2. updated dc characteristics for at83snd1c product. 27.3 changes from 4109f-01/04 to 4109g- 07/04 1. uart bootloader now flagged as option in features section. 2. add usb connection schematic in usb section. 3. add usb termination characteristics in dc characteristics section. 4. page access mode clarification in data memory section. 27.4 changes from 4109g-07/04 to 4109h- 01/05 1. clarify ea pin not present on packages but on dice. 2. interrupt priority number clarification to match number defined by development tools
211 at8xc51snd1c 4109h?8051?01/05
table of contents i 1. features ............................................................................................. 1 2. description ........................................................................................ 2 3. typical applications ......................................................................... 2 4. block diagram ................................................................................... 2 5. pin description .................................................................................. 3 5.1 pinouts ........................................................................................................... 3 5.2 signals............................................................................................................. 6 5.3 internal pin structure.................................................................................... 11 6. clock controller .............................................................................. 12 6.1 oscillator ...................................................................................................... 12 6.2 x2 feature.................................................................................................... 12 6.3 pll ............................................................................................................... 13 6.4 registers ....................................................................................................... 15 7. program/code memory .................................................................. 17 7.1 romless memory architecture................................................................... 18 7.2 rom memory architecture ........................................................................... 19 7.3 flash memory architecture .......................................................................... 19 7.4 hardware security system ............................................................................ 21 7.5 boot memory execution ............................................................................... 21 7.6 preventing flash corruption......................................................................... 22 7.7 registers ....................................................................................................... 23 7.8 hardware bytes ............................................................................................. 24 8. data memory ................................................................................... 25 8.1 internal space .............................................................................................. 25 8.2 external space .............................................................................................. 27 8.3 dual data pointer ......................................................................................... 29 8.4 registers ...................................................................................................... 30 9. special function registers ............................................................ 32 10. interrupt system ........................................................................... 38 10.1 interrupt system priorities .......................................................................... 38 10.2 external interrupts ...................................................................................... 41 10.3 registers ..................................................................................................... 42
ii at8xc51snd1c 4109h?8051?01/05 11. power management ...................................................................... 48 11.1 reset .......................................................................................................... 48 11.2 reset recommendation to prevent flash corruption ................................ 49 11.3 idle mode .................................................................................................... 49 11.4 power-down mode...................................................................................... 50 11.5 registers......................................................................................................52 12. timers/counters ........................................................................... 53 12.1 timer/counter operations .......................................................................... 53 12.2 timer clock controller ................................................................................ 53 12.3 timer 0........................................................................................................ 54 12.4 timer 1........................................................................................................ 56 12.5 interrupt ...................................................................................................... 57 12.6 registers......................................................................................................58 13. watchdog timer ............................................................................ 61 13.1 description.................................................................................................. 61 13.2 watchdog clock controller ......................................................................... 61 13.3 watchdog operation....................................................................................62 13.4 registers......................................................................................................63 14. mp3 decoder ................................................................................. 64 14.1 decoder ...................................................................................................... 64 14.2 audio controls .............................................................................................66 14.3 decoding errors.......................................................................................... 66 14.4 frame information .......................................................................................67 14.5 ancillary data.............................................................................................. 67 14.6 interrupt .......................................................................................................68 14.7 registers......................................................................................................70 15. audio output interface ................................................................. 75 15.1 description.................................................................................................. 75 15.2 clock generator...........................................................................................76 15.3 data converter ........................................................................................... 76 15.4 audio buffer ................................................................................................ 77 15.5 mp3 buffer.................................................................................................. 78 15.6 interrupt request ........................................................................................ 78 15.7 mp3 song playing ...................................................................................... 78 15.8 voice or sound playing .............................................................................. 79 15.9 registers......................................................................................................80 16. universal serial bus ..................................................................... 82 16.1 description...................................................................................................83 16.2 configuration .............................................................................................. 86 16.3 read/write data fifo ................................................................................ 88 16.4 bulk/interrupt transactions......................................................................... 89
iii at8xc51snd1c 4109h?8051?01/05 16.5 control transactions................................................................................... 93 16.6 isochronous transactions............................................................................94 16.7 miscellaneous ..............................................................................................96 16.8 suspend/resume management ..................................................................97 16.9 usb interrupt system ................................................................................. 99 16.10 registers..................................................................................................101 17. multimedia card controller ........................................................ 111 17.1 card concept............................................................................................ 111 17.2 bus concept ............................................................................................. 111 17.3 description................................................................................................ 116 17.4 clock generator........................................................................................ 116 17.5 command line controller......................................................................... 118 17.6 data line controller...................................................................................120 17.7 interrupt .....................................................................................................126 17.8 registers....................................................................................................127 18. ide/atapi interface .................................................................... 133 18.1 description................................................................................................ 133 18.2 registers................................................................................................... 135 19. serial i/o port .............................................................................. 136 19.1 mode selection ......................................................................................... 136 19.2 baud rate generator................................................................................ 136 19.3 synchronous mode (mode 0) ................................................................... 137 19.4 asynchronous modes (modes 1, 2 and 3) .................................................139 19.5 multiprocessor communication (modes 2 and 3) ..................................... 142 19.6 automatic address recognition................................................................ 142 19.7 interrupt .....................................................................................................145 19.8 registers....................................................................................................146 20. synchronous peripheral interface ............................................ 149 20.1 description.................................................................................................150 20.2 interrupt .................................................................................................... 154 20.3 configuration .............................................................................................155 20.4 registers....................................................................................................159 21. two-wire interface (twi) controller .......................................... 161 21.1 description................................................................................................ 161 21.2 registers................................................................................................... 175 22. analog to digital converter ....................................................... 177 22.1 description................................................................................................ 177 22.2 registers....................................................................................................180 23. keyboard interface ..................................................................... 182
iv at8xc51snd1c 4109h?8051?01/05 23.1 description................................................................................................ 182 23.2 registers....................................................................................................183 24. electrical characteristics ........................................................... 184 24.1 absolute maximum rating........................................................................ 184 24.2 dc characteristics.................................................................................... 184 24.3 ac characteristics .................................................................................... 189 24.4 spi interface ............................................................................................. 195 25. ordering information .................................................................. 206 26. package information .................................................................. 207 26.1 tqfp80 .................................................................................................... 207 26.2 bga81 ...................................................................................................... 208 26.3 plcc84 .................................................................................................... 209 27. datasheet change log for at8xc51snd1c ............................ 210 27.1 changes from 4109d-10/02 to 4109e-06/03............................................ 210 27.2 changes from 4109e-06/03 to 4109f-01/04 ............................................ 210 27.3 changes from 4109f-01/04 to 4109g-07/04............................................ 210 27.4 changes from 4109g-07/04 to 4109h-01/05 ........................................... 210
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